Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Disclosed are a magnetic device and a method of manufacturing the same. The magnetic device includes an insulation spacer that surrounds a portion of a wiring structure and a variable resistance structure. In order to manufacture the magnetic device, a magnetic resistance element and an electrode covering the magnetic resistance element are formed on a substrate by using a sacrificial mask pattern as an etch mask, and then, an insulation spacer that surrounds the magnetic resistance element, the electrode, and the sacrificial mask pattern and exposes the sacrificial mask pattern is formed. A contact space that is limited by the insulation spacer and exposes the electrode is provided by removing the sacrificial mask pattern. A conductive pattern contacting the electrode is formed in the contact space.

Abstract: In one embodiment, there is provided a non-volatile magnetic memory cell. The non-volatile magnetic memory cell comprises a switchable magnetic element; and a word line and a bit line to energize the switchable magnetic element; wherein at least one of the word line and the bit line comprises a magnetic sidewall that is discontinuous.

Abstract: An electronic device in accordance with this technology includes semiconductor memory. The semiconductor memory may include a magnetization-pinned layer configured to include a first magnetic layer, a second magnetic layer, and a non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, a free magnetization layer spaced apart from the magnetization-pinned layer, a tunnel barrier layer interposed between the magnetization-pinned layer and the free magnetization layer, and a magnetic spacer configured to come in contact with a side of the first magnetic layer and at least part of a side of the second magnetic layer.

Abstract: A thermally-assisted magnetic writing device includes at least one magnetic element including: a reference layer having a stable vortex magnetization configuration; a device to create a magnetic field to reversibly move the vortex core in the plane of the reference layer; a storage layer having a variable magnetization configuration; a non-magnetic spacer that separates and magnetically decouples the reference layer and the storage layer; an antiferromagnetic pinning layer in contact with the storage layer, the antiferromagnetic layer being capable of pinning the magnetization configuration of the storage layer, the storage layer having at least two storage levels corresponding to two pinned magnetization configurations; a device to heat the antiferromagnetic pinning layer such that when heated, the temperature of the antiferromagnetic pinning layer exceeds its blocking temperature such that the magnetization configuration of the storage layer is no longer pinned when warm.

Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage.

Abstract: A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.

Abstract: A mechanism relates to magnetic random access memory (MRAM). A free magnetic layer is provided and first fixed layers are disposed above the free magnetic layer. Second fixed layers are disposed below the free magnetic layer. The first fixed layers and the second fixed layers both comprise a rare earth element.

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

Abstract: A magnetic element and a magnetic memory utilizing the magnetic element are described. A contact is electrically coupled to the magnetic element. The magnetic element includes pinned, nonmagnetic spacer, and free layers and a perpendicular capping layer adjoining the free layer and the contact. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy. The free layer is switchable between magnetic states when a write current is passed through the magnetic element. The free layer includes ferromagnetic layers interleaved with capping layer(s) such that a ferromagnetic layer resides at an edge of the free layer.

Abstract: A method for fabricating a magnetic tunnel junction cell includes steps of providing a substrate having an active surface, forming a tunnel layer, a fixed layer and a first electrode, forming a U-shaped free layer having a vertical portion substantially perpendicular to the active surface, and forming a second electrode embedded in the U-shaped free layer. The fixed layer lines an inner surface of a through hole substantially perpendicular to the active surface and the first electrode fills the through hole. The tunnel layer may line the inner surface of the through hole or be U-shaped lining an inner surface of the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer constitute a magnetic tunnel junction.

Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Abstract: According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

Abstract: A logic unit for security engines or content addressable memory including Magnetic Tunnel Junction (MTJ) elements connected in series to form a NAND-type string, where each MTJ element includes a storage layer and a sense layer having different anti-ferromagnetic materials respectively having higher and lower blocking temperatures. During write/program, the string is heated above the higher blocking temperature, and magnetic fields are used to store bit values of a confidential logical pattern in the storage layers. The string is then cooled to an intermediate temperature between the higher and lower blocking temperatures and the field lines turned off to store bit-bar (opposite) values in the sense layers. During a pre-compare operation, the MTJ elements are heated to the intermediate temperature, and an input logical pattern is stored in the sense layers. During a compare operation, with the field lines off, a read current is passed through the string and measured.

Abstract: In one aspect, a nonvolatile magnetic logic device comprises an electrically insulating layer, a write path, and a read path. The write path comprises a plurality of write path terminals and a magnetic layer having a uniform magnetization direction that is indicative of a direction of magnetization of the magnetic layer in a steady state. A logic state is written to the nonvolatile magnetic logic device by passing a current through the plurality of write path terminals. The read path comprises a plurality of read path terminals for evaluation of the logic state. The electrically insulating layer promotes electrical isolation between the read path and the write path and magnetic coupling of the read path to the write path.

Abstract: A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.

Abstract: According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.

Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.

Abstract: One embodiment includes a metal layer including first and second metal portions; a ferromagnetic layer including a first ferromagnetic portion that directly contacts the first metal portion and a second ferromagnetic portion that directly contacts the second metal portion; and a first metal non-magnetic interconnect coupling the first ferromagnetic portion to the second ferromagnetic portion. The spin interconnect conveys spin polarized current suitable for spin logic circuits. The interconnect may be included in a current repeater such as an inverter or buffer. The interconnect may perform regeneration of spin signals. Some embodiments extend spin interconnects into three dimensions (e.g., vertically across layers of a device) using vertical non-magnetic metal interconnects.

Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.

Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Abstract: A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer.

Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, at least one insulating layer, and at least one magnetic insertion layer adjoining the at least one insulating layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one insulating layer is adjacent to at least one of the free layer and the pinned layer. The at least one magnetic insertion layer adjoins the at least one insulating layer. In some aspects, the insulating layer(s) include at least one of magnesium oxide, aluminum oxide, tantalum oxide, ruthenium oxide, titanium oxide, and nickel oxide The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, and at least one damping reduction layer. The free layer has an intrinsic damping constant. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one damping reduction layer is adjacent to at least a portion of the free layer and configured to reduce the intrinsic damping constant of the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A magnetic junction is described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The magnetic junction may also include an additional nonmagnetic spacer layer and an additional pinned layer opposing the nonmagnetic spacer layer and the pinned layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer is configured to be switchable using a write current passed through the magnetic junction. The free layer is also configured to be thermally stable in a quiescent state and have a reduced thermal stability due to heating from the write current being passed through the magnetic junction. In some aspects, the free layer includes at least one of a pinning layer(s) interleaved with ferromagnetic layer(s), two sets of interleaved ferromagnetic layers having different Curie temperatures, and a ferrimagnet having a saturation magnetization that increases with temperature between ferromagnetic layers.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: The invention relates to a magnetic sensor and a magnetic memory which sense magnetic information held by a ferromagnetic body without a current flowing through the ferromagnetic body. The magnetic sensor and magnetic memory use a magnetoresistive effect generated in a current that flows through a metal layer along an interface, on at least the interface side, with a ferromagnetic dielectric layer and said metal layer being joined through said interface.

Abstract: A magnetic pressure sensor is provided that includes a semiconductor body with a top side and a back side, a Hall sensor formed on the top side of the semiconductor body, a spacer connected to the semiconductor body, whereby the spacer has a recess in the center, and a membrane covering the recess, whereby the membrane has a first material and has a ferromagnetic substance. The ferromagnetic substance concentrates a magnetic flux density of a source formed outside the ferromagnetic material, and the spacer is formed as a circumferential wall and has a second material and the second material is different from the first material in at least one element.

Abstract: A semiconductor device includes a Hall element, which is switched between a first and second mode. In the first mode, connection A between a first and second resistor and connection C between a third and fourth resistor are set to Vcc or GND. Connection D between the first and fourth resistor and connection B between the second and third resistor are set as output terminals. In the second mode, D and B are set to Vcc or GND and A and C are set as output terminals. When a first line placed along the second resistor and connected to A is set at Vcc in the first mode, a second line placed along the fourth resistor and connected to D is set at Vcc in the second mode. When the first line is set at GND in first mode, the second line is set at GND in the second mode.

Abstract: The disclosure provides a non-volatile memory structure and a method for fabricating the same. The non-volatile memory structure includes a first contact connected to a first transistor. A second contact is connected to a second transistor. A resistance-changing memory material pattern covers and contacts the second contact but not the first contact. A top electrode contacts both the resistance-changing memory material pattern and the first contact. An area of the resistance-changing memory material pattern is substantially larger than an area of its interface with the second contact.

Abstract: An embodiment of the invention includes a memory cell having a magnet layer coupled to a metal layer and read line. The metal layer is also coupled to write and sense lines. During a write operation charge current is supplied to the metal layer via the write line and induces spin current and a magnetic state within the magnet layer based on the spin Hall effect. During a read operation read current is supplied, via the read line, to the magnet layer and then the metal layer and induces another spin current, within the metal layer, that generates an electric field and voltage, based on inverse spin Hall effect, at a sense node coupled to the sense line. The voltage polarity is based on the aforementioned magnetic state. The memory operates with a low supply voltage to drive charge, read, and spin currents. Other embodiments are described herein.

Abstract: Multi-period structures exhibiting giant magnetoresistance (GMR) are described in which the exchange coupling across the active interfaces of the structure is ferromagnetic.

Abstract: A vertical Hall sensor includes first and second vertical Hall effect regions in a semiconductor substrate, with first and second pluralities of contacts arranged at one side of the first or second vertical Hall effect regions, respectively. The second vertical Hall effect region is connected in series with the first vertical Hall effect region regarding a power supply. The vertical Hall sensor further includes first and second layers adjacent to the first and second vertical Hall effect regions at a side other than a side of the first or second pluralities of contacts. The first and second layers have different doping properties than the first and second vertical Hall effect regions and insulate the first and second vertical Hall effect regions from a bulk of the semiconductor substrate by at least one reverse-biased p-n junction per vertical Hall effect region during an operation of the vertical Hall sensor.

Abstract: A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.

Abstract: A method of fabricating a magnetic memory according to an embodiment includes: forming a separation layer on a first substrate; sequentially forming a first ferromagnetic layer, a first nonmagnetic layer, and a second ferromagnetic layer on the separation layer, at least one of the first and the second ferromagnetic layers having a single crystal structure; forming a first conductive bonding layer on the second ferromagnetic layer; forming a second conductive bonding layer on a second substrate, on which a transistor and a wiring are formed, the second conductive bonding layer electrically connecting to the transistor; arranging the first and second substrate so that the first conductive bonding layer and the second conductive bonding layer are opposed to each other, and bonding the first and the second conductive bonding layers to each other; and separating the first substrate from the first ferromagnetic layer by using the separation layer.

Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Abstract: Apparatus and methods of manufacturing an image sensor and inertial navigation sensors encapsulated within a single package. The single package may encapsulate one integrated circuit die comprising the imaging sensor and the inertial navigation sensors. Alternatively, the single package may encapsulate a plurality of integrated circuit dice comprising the imaging sensor and the inertial navigation sensors.

Abstract: A magnetic junction is described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The magnetic junction may also include an additional nonmagnetic spacer layer and an additional pinned layer opposing the nonmagnetic spacer layer and the pinned layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer is configured to be switchable using a write current passed through the magnetic junction. The free layer is also configured to be thermally stable in a quiescent state and have a reduced thermal stability due to heating from the write current being passed through the magnetic junction. In some aspects, the free layer includes at least one of a pinning layer(s) interleaved with ferromagnetic layer(s), two sets of interleaved ferromagnetic layers having different Curie temperatures, and a ferrimagnet having a saturation magnetization that increases with temperature between ferromagnetic layers.

Abstract: A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H2 gas.

Abstract: An inductor in a semiconductor device may include a first interconnection line on a substrate; a second interconnection line on the first interconnection line; first and second common interconnection lines on the second interconnection line; a first via connecting a first end of the first interconnection line to a first end of the first common interconnection line; a second via connecting a second end of the first interconnection line to a second end of the second common interconnection line; a third via connecting a first end of the second interconnection line to the first end of the first common interconnection line; and a fourth via connecting a second end of the second interconnection line to the second end of the second common interconnection line. The first and second interconnection lines and the first and second common interconnection lines may extend in a direction parallel to a surface of the substrate.

Abstract: Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract: An apparatus may include a back-bias magnet; and a semiconductor chip element; wherein the semiconductor chip element has a sensor for measuring a magnetic field strength; and wherein a contact surface is formed on a contact side of the back-bias magnet and on a contact side of the semiconductor chip element and wherein the contact side of the semiconductor chip element has one or more structures such that the contact surface of the back-bias magnet is shaped in a manner corresponding to the structures of the semiconductor chip element.

Abstract: According to one embodiment, a magnetoresistive element comprises a first magnetic layer having a magnetization direction invariable and perpendicular to a film surface, a tunnel barrier layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel barrier layer and having a magnetization direction variable and perpendicular to the film surface. The first magnetic layer includes an interface layer formed on an upper side in contact with a lower portion of the tunnel barrier layer, and a main body layer formed on a lower side and serving as an origin of perpendicular magnetic anisotropy. The interface layer includes a first area provided on an inner side and having magnetization, and a second area provided on an outer side to surround the first area and having magnetization smaller than the magnetization of the first area or no magnetization.

Abstract: An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element.

Abstract: A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.

Abstract: Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).