Abstract: A microelectromechanical systems (MEMS) die comprises a first diaphragm having a first side and a second side, and a second diaphragm having a first side facing the first side of the first diaphragm. A first plurality of interconnect strips is disposed along at least the first side of the first diaphragm, a second plurality of interconnect strips is disposed along the first side of the first diaphragm, and a third plurality of interconnect strips is disposed along the first side of the second diaphragm. First, second, and third runner strips are disposed along the second side of the first diaphragm transverse to the first, second, and third plurality of interconnect strips, respectively. Each of the first, second, and third runner strips is electrically connected to at least a subset of the first, second, and third plurality of interconnect strips, respectively, via electrical connections disposed through the first diaphragm.

Abstract: A bonded substrate includes: a first substrate; and a second substrate having a bonding surface bonded to the first substrate, wherein the second substrate includes a recess having a bottom surface recessed from a surface opposite to the bonding surface, and a difference between the maximum height and the minimum height of the bottom surface from the surface opposite to the bonding surface of the recess is less than 10 ?m.

Abstract: A MEMS optical device having an optically active portion and an actuation portion adjacent to each other. The MEMS optical device includes a body, a piezoelectric actuator, and a cap. The body is formed by a substrate, housing a cavity containing a fluid and by a deformable region fixed to the substrate, suspended over the cavity and forming a membrane. The piezoelectric actuator extends on the deformable region at the actuation portion and is protected by the cap, which is coupled to the body at the actuation portion and defines a chamber that houses the piezoelectric actuator.

Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

Abstract: The invention provides a planarization method, which can make the local flatness of the product to be processed more uniform. The product has a cavity filled with oxide and includes a first electrode layer, a piezoelectric layer and a second electrode layer superposed on the cavity. The first electrode layer covers the cavity and includes a first inclined face around the first electrode layer, and the piezoelectric layer covers the first electrode layer and is arranged on the first electrode layer. The planarization method includes: depositing a passivation layer on the second electrode layer and etching the passivation layer completely until the thickness of the passivation layer is reduced to the required thickness.

Abstract: Technologies are provided for microelectromechanical microphones that can be robust to substantial pressure changes in the environment in which the micromechanical microphones operate. In some embodiments, a microelectromechanical microphone device can include a substrate defining a first opening to receive a pressure wave. The microelectromechanical microphone device also can include a flexible plate mechanically coupled to the substrate and a rigid plate mechanically coupled to the flexible plate. The flexible plate is deformable by the pressure wave. The rigid plate defines multiple openings that permit passage of the pressure wave. The microelectromechanical microphone device can further include at least one stoppage member assembled in a spatial relationship with the flexible plate. The at least one stoppage member can limit motion of the flexible plate in response to the pressure wave including a threshold amplitude.

Abstract: A sensor device includes a microelectromechanical system (MEMS) force sensor, and a capacitive acceleration sensor. In the method of manufacturing the sensor device, a sensor portion of the MEMS force sensor is prepared over a front surface of a first substrate. The sensor portion includes a piezo-resistive element and a front electrode. A bottom electrode and a first electrode are formed on a back surface of the first substrate. A second substrate having an electrode pad and a second electrode to the bottom of the first substrate are attached such that the bottom electrode is connected to the electrode pad and the first electrode faces the second electrode with a space therebetween.

Abstract: A detecting device 100 detects an elastic wave propagating through the air. The detecting device 100 includes: a first electrode 12 that is a plate having a cantilever structure with a fixed end FX and a free end FR and that vibrates by being bent by the elastic wave; and a second electrode 32 that is a plate, that is opposed to the first electrode, and that has a predetermined distance from the first electrode. The detecting device 100 detects the elastic wave on the basis of a change in capacitance between the first electrode and the second electrode 32. An end of the second electrode 32 in a direction from the fixed end FX to the free end FR is closer to the fixed end than the free end.

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.

Abstract: A display device may include a first substrate, a touch sensor disposed on the first substrate, a second substrate disposed on the touch sensor, and a display unit disposed on the second substrate and which displays an image. The touch sensor includes a piezoelectric device, which senses a touch thereon, and an adhesive layer, which attaches the first and second substrates to each other. The piezoelectric device and the adhesive layer are disposed in a same layer.

Abstract: An ultrasonic probe includes a capacitive micromachined ultrasonic transducer (cMUT) array configured to generate ultrasonic waves, an integrated circuit to which the cMUT array is bonded, and a flexible printed circuit board having one end connected to the integrated circuit to output signals to the integrated circuit, the integrated circuit including pads provided on the integrated circuit and an anisotropic conductive film (ACF) provided on the pads, and the one end of the flexible printed circuit board being connected to the ACF to thereby connect the flexible printed circuit board to the integrated circuit.

Abstract: A semiconductor differential pressure sensor element is such that as strain sensitive elements are disposed only inside a diaphragm, and strain relaxation grooves are provided along the diaphragm, it is difficult for thermal stress caused by expansion or contraction of a case to propagate to the strain sensitive elements, thus suppressing characteristic fluctuations resulting from a change in external temperature. Also, as a configuration is such that a sacrificial column is provided inside a depressed portion, and that the diaphragm is held by the sacrificial column in a diaphragm formation step which thins a second semiconductor substrate and a functional element formation step which repeatedly implements a cleaning step, breakage of the diaphragm can be prevented, thus achieving a significant improvement in yield.

Abstract: A fingerprint sensor for sensing fingerprint information of a finger is provided. The fingerprint sensor includes a sensing array including a plurality of sensing units, an insulating surface disposed on the sensing array, a readout module, a memory array including a plurality of memory units respectively corresponding to the sensing units, and a processor. Each of the sensing units includes a sensing electrode. The readout module reads a sensing voltage of the sensing electrode of each of the sensing units, and provides a sensing output according to the sensing voltage. Each of the memory units is adjacent to the corresponding sensing unit and stores information of the corresponding sensing unit. The processor obtains the fingerprint information of the finger according to the sensing output and the information stored in the memory unit.

Abstract: An ultrasonic sensor includes: a substrate disposed across an XY plane; a plurality of spaces formed in the substrate in at least one direction of an X-axis direction and a Y-axis direction; a vibrating plate that is provided on the substrate such that the spaces are enclosed and that has a first surface on the substrate side and a second surface facing the first surface; a piezoelectric element that is provided at a portion on the second surface side of the vibrating plate that corresponds to the space and that transmits and/or receives an ultrasonic wave; a surrounding plate that is provided on the second surface side of the vibrating plate and surrounds a peripheral region of the piezoelectric element; and a support member provided at a position, at which the support member is not overlapped with the piezoelectric element, between a surface of the surrounding plate on the piezoelectric element side and the second surface of the vibrating plate.

Abstract: Provided is a fingerprint sensor. The fingerprint sensor according to an embodiment of the inventive concept includes a plurality of transmission lines, a plurality of receive lines, and a sensor array including sensor units connected to the plurality of transmission lines. Each of the sensor units includes a switch transistor having a gate terminal and one terminal, which are commonly connected to a corresponding transmission line of the plurality of transmission lines and a sensor transistor connected between the other end of the switch transistor and a corresponding receive line of the plurality of receive lines. The sensor transistor performs a current suppression on in response to a voltage of a virtual gate that is touched by a fingerprint.

Abstract: A functional micromechanical timepiece assembly including at least a first component, including a first layer defining a first contact surface configured to come into friction contact with a second contact surface defined by a second layer, the second layer belonging, either to the first component, or to at least a second micromechanical component forming the assembly with the first component. The first and second layers each include carbon with at least 50% carbon atoms and, on the first and second contact surfaces, the layers have different surface crystalline plane orientations from each other.

Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

Abstract: Provided is a contact force sensor of high sensitivity and high accuracy. This contact force sensor is fabricated by machining of a silicon semiconductor material. The contact force sensor is provided with a sensor configuration having a base part, and a contact force transmission part formed in a direction orthogonal to this base part. A stress-electricity conversion element for converting displacement of the contact force transmission part to an electrical signal, formed in the base part of the sensor configuration, is also provided.

Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

Abstract: A touch panel comprises a plurality of basic sensing-units arranged in a matrix. The basic sensing-unit comprises a pressure-sensing transistor and a selection transistor. The pressure-sensing transistor comprises a first terminal, a second terminal, a gate electrode, a mask layer, a channel connecting the first and second terminals, a dielectric layer formed on the channel, and a piezoelectric material deposited on the dielectric layer. The piezoelectric material may comprise PVDF, lead zirconate titanate, ZnO, BaTiO3, LiNbO3, or PbTiO3. The selection transistor comprises a first terminal, a second terminal, and a third terminal. The first terminal of the selection transistor connects to a sensing electrode of the touch panel, the second terminal of the selection transistor connects to the first terminal of the pressure sensing transistor, and the third terminal of the selection transistor is a transistor gate and connects to a drive electrode of the touch panel.

Abstract: The present disclosure is directed to a device that includes a substrate and a sensor formed on the substrate. The sensor includes a chamber formed from a plurality of integrated cavities, a membrane above the substrate, the membrane having a plurality of openings, each opening positioned above one of the cavities, and a plurality of diamond shaped anchors positioned between the membrane and the substrate, the anchors positioned between each of the cavities. A center of each opening is also a center of one of the cavities.

Abstract: The micro-electromechanical semiconductor component is provided with a semiconductor substrate in which a cavity is formed, which is delimited by lateral walls and by a top and a bottom wall. In order to form a flexible connection to the region of the semiconductor substrate, the top or bottom wall is provided with trenches around the cavity, and bending webs are formed between said trenches. At least one measuring element that is sensitive to mechanical stresses is formed within at least one of said bending webs. Within the central region surrounded by the trenches, the top or bottom wall comprises a plurality of depressions reducing the mass of the central region and a plurality of stiffening braces separating the depressions.

Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms.

Abstract: A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell.

Abstract: A pressure sensor device is assembled by forming cavities on a surface of a metal sheet and then forming an electrically conductive pattern having traces and bumps over the cavities. An insulating layer is formed on top of the pattern and then processed to form exposed areas and die attach areas on the surface of the metal sheet. The exposed areas are plated with a conductive metal and then electrically connected to respective ones of the bumps. A gel is dispensed on the die attach areas and sensor dies are attached to respective die attach areas. One or more additional semiconductor dies are attached to the insulating layer and bond pads of these dies are electrically connected to the exposed plated areas. A molding compound is dispensed such that it covers the sensor die and the additional dies. The metal sheet is removed to expose outer surfaces of the bumps.

Abstract: A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Abstract: A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROMB) is disclosed. It can achieve large bit-per-cell (e.g. 4-bpc or more). 3D-MPROMB can be realized by adding resistive layer(s) or resistive element(s) to the memory cells.

Abstract: A multi-chip push-pull magnetoresistive bridge sensor utilizing magnetic tunnel junctions is disclosed. The magnetoresistive bridge sensor is composed of a two or more magnetic tunnel junction sensor chips placed in a semiconductor package. For each sensing axis parallel to the surface of the semiconductor package, the sensor chips are aligned with their reference directions in opposition to each other. The sensor chips are then interconnected as a push-pull half-bridge or Wheatstone bridge using wire bonding. The chips are wire-bonded to any of various standard semiconductor lead frames and packaged in inexpensive standard semiconductor packages.

Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.

Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face and becomes a reference for the information stored in the memory layer; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer and is formed of a non-magnetic layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure having the memory layer, the insulating layer, and the magnetization-fixed layer, and thereby the magnetization direction varies and a recording of information is performed with respect to the memory layer, and a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer.

Abstract: A finger sensing device may include a mounting substrate, an integrated circuit (IC) die carried by the mounting substrate and having an array of electric field-based finger sensing elements, and first electrical connections coupling the mounting substrate and the IC die. In addition, the finger sensing device may include a protective plate attached over the array of electric field-based finger sensing elements and having a dielectric constant greater than 5 in all directions and a thickness greater than 40 microns to define a capacitive lens for the array of electric field-based finger sensing elements. The finger sensing device may also include an encapsulating material adjacent the mounting substrate and the IC die and around at least the first electrical connections.

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: A magnetoresistive element includes: a lower magnetic layer; a barrier layer; and an upper magnetic layer. The barrier layer is provided on the lower magnetic layer. The upper magnetic layer is provided on the barrier layer. One of magnetization directions of the lower magnetic layer and the upper magnetic layer is fixed. The barrier layer has a first surface which includes a surface contacted with an upper surface of the lower magnetic layer. The upper magnetic layer has a second surface which includes a surface contacted with an upper surface of the barrier layer. Each of the first surface and the second surface is larger than the upper surface of the lower magnetic layer in area.

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer has an engineered perpendicular magnetic anisotropy. The engineered PMA includes at least one of an insulating insertion layer induced PMA, a stress induced PMA, PMA due to interface symmetry breaking, and a lattice mismatch induced PMA. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

Abstract: An electrically insulating sheathing for a piezoresistor and a semiconductor material are provided such that the piezoresistor is able to be used in the high temperature range, e.g., for measurements at higher ambient temperatures than 200° C. A doped resistance area is initially laterally delineated by at least one circumferential essentially vertical trench and is undercut by etching over the entire area. An electrically insulating layer is then created on the wall of the trench and the undercut area, so that the resistance area is electrically insulated from the adjacent semiconductor material by the electrically insulating layer.

Abstract: A piezoelectric device includes an integrated circuit (IC) chip and a piezoelectric resonator element, a part of the piezoelectric resonator element being disposed so as to overlap with a part of the IC chip when viewed in plan. The IC chip includes: an inner pad disposed on an active face and in an area where is overlapped with the piezoelectric resonator when viewed in plan; an insulating layer formed on the active face; a relocation pad disposed on the insulating layer and in an area other than a part where is overlapped with the piezoelectric resonator element, the relocation pad being coupled to an end part of a first wire; and a second wire electrically coupling the inner pad and the relocation pad, the second wire having a relocation wire and a connector that penetrates the insulating layer, the relocation wire being disposed between the insulating layer and the active face.

Abstract: Disclosed are a ReRAM, which is a non-volatile memory device, and a production method therefor. A resistance-variable layer, which varies the resistance in accordance with an applied pulse, has a multilayered structure comprising 3 oxide films. Each oxide film consists of an oxide film of the same type as the neighbouring oxide film(s), but the oxygen ratios in the compositions of neighbouring oxide films differ from each other.

Abstract: A magnetic body device has a stacked structure comprising an underlying layer, a magnetic body layer, and a cap layer. The material for the underlying layer is different from that for the cap layer. The magnetic body layer has a free magnetization region having perpendicular magnetic anisotropy and a first characteristic change region and a second characteristic change region situated on both sides of the free magnetization region in a first in-plane direction. The perpendicular magnetic anisotropy of the first characteristic change region and the second characteristic change region is at a level lower than that of the free magnetization region. An external magnetic field containing a component in the first in-plane direction is applied to the free magnetization region. Further, a current in the first in-plane direction is supplied to the free magnetization region.

Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.