Abstract: A sensor chip assembly for use in a sensor capable of Surface Plasmon Resonance (SPR) and gravimetric sensing. The assembly comprising a transparent piezoelectric substrate (I) having a first surface and a second surface opposite to the first surface. The assembly also comprising first and second thin film metal electrodes (2,3) respectively provided on the first and second surfaces of the substrate (1). The second thin film metal electrode (3) being position on the second surface of the substrate (1) such that a light beam is capable of being transmitted through the second surface of the substrate and reflected from the first thin film metal electrode. The assembly also comprising an attenuated total reflection (ATR) coupler (11) disposed adjacent to the second thin film metal electrode (3).

Abstract: An aspect of the present invention is a thin film device. The thin film device includes at least one patterned thin film layer, a thermally conductive material coupled to at least one of the patterned thin-film layer and an electrically and thermally isolating material in contact with the thermally conductive material.

Abstract: A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

Abstract: An MTJ MRAM cell is formed between ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately two for a given current. Because the lines require thinner depositions, there is no necessity of removing material by CMP during patterning and polishing. Therefore, there is a uniform spacing between the lines and the cell free layer.

Abstract: Provided is a method of fabricating a near-field optical probe adapted to a near-field scanning optical microscopy and a near-field information storage device, in which a cantilever and an optical tip are provided in one body and the optical tip is arranged to face the upper portion of the substrate. High-concentrated boron ions are implanted into an uppermost silicon layer of a silicon on insulator (SOI) substrate, and a silicon layer into which boron ions are implanted while the silicon inside the tip is etched to form the hole to act as an etch stop layer, thereby easily removing the silicon inside the tip even with the cantilever exposed, and simplifying the process due to the simultaneous fabrication of the cantilever and the tip.

Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

Abstract: A method of isolating piezoelectric thin film acoustic resonator devices to prevent laterally propagating waves generated by the device from leaving the device and/or interfering with adjacent devices or systems. Specifically, this isolation technique involves the manipulation or isolation of the piezoelectric material layer between the acoustic resonator devices, in an effort to limit the amount of acoustic energy which propagates in a lateral direction away from the device. In one aspect, at least a portion of the piezoelectric material not involved in signal transmission by transduction between RF and acoustic energy is removed from the device. In another aspect, the growth a piezoelectric material is limited to certain regions during fabrication of the device. In a further aspect, the crystal orientation of the piezoelectric material is disrupted or altered during device fabrication so as to form regions having excellent piezoelectric properties and regions exhibiting poor piezoelectric characteristics.

Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Abstract: A memory cell structure. A first conductive line is cladded by at least two first ferromagnetic layers respectively having a first easy axis and a second easy axis, a nano oxide layer located between the first ferromagnetic layers, and a first pinned ferromagnetic layer. The first and second easy axes are 90 degree twisted-coupled with the first easy axis parallel to the length of the first conductive line and the second easy axis perpendicular to the length of the first conductive line. A storage device is adjacent to the first conductive line, receiving a magnetic field generated from a current flowing through the first conductive line.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract: An MRAM array is formed of MTJ cells shaped so as to have their narrowest dimension at the middle of the cell. A preferred embodiment forms the cell into the shape of a kidney or a peanut. Such a shape provides each cell with an artificial nucleation site at the narrowest dimension, where an applied switching field can switch the magnetization of the cell in manner that is both efficient and uniform across the array.

Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.

Abstract: A magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate, with each memory stack having two memory cells stacked along the Z axis and each memory cell having an associated biasing layer. Each biasing layer reduces the switching field of its associated cell by applying a biasing field along the hard-axis of magnetization of the free layer of its associated cell. The free layers in the two cells in each stack have their in-plane easy axes of magnetization aligned parallel to one another. Each biasing layer has its in-plane magnetization direction oriented perpendicular to the easy axis of magnetization (and thus parallel to the hard axis) of the free layer in its associated cell. The hard-axis biasing fields generated by the two biasing layers are in opposite directions.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7?X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1?XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Abstract: Disclosed is a magnetic memory apparatus which comprises a patterned magnetic recording medium in which multilayered films each having a first magnetic layer, a nonmagnetic metal layer or a nonmagnetic insulating layer and a second magnetic layer deposited discretely on a conductive electrode layer formed on a substrate, and a cantilever array having a plurality of cantilevers each having a conductive chip at its distal end. This provides a magnetic solid memory apparatus that has a large memory capacity and a super fast transfer rate, the merits of a hard disk apparatus, and a nanostructure and low power consumption, which are the merits of a semiconductor memory.

Abstract: An apparatus and method for sensor architecture based on bulk machining of Silicon-On-Oxide wafers and fusion bonding that provides a symmetric, nearly all-silicon, hermetically sealed MEMS device having a sensor mechanism formed in an active semiconductor layer, and opposing silicon cover plates each having active layers bonded to opposite faces of the sensor mechanism. The mechanism is structured with sensor mechanical features structurally supported by at least one mechanism anchor. The active layers of the cover plates each include interior features structured to cooperate with the sensor mechanical features and an anchor structured to cooperate with the mechanism anchor. A handle layer of each cover plate includes a pit extending there through in alignment with the cover plate anchor. An unbroken rim of dielectric material forms a seal between the cover plate anchor and the pit and exposes an external surface of the cover plate anchor.

Abstract: A magnetic random access memory according to an example of the present invention includes a magnetoresistive element, a write line for use in generation of a magnetic field for data writing with respect to the magnetoresistive element, and a strained layer which is disposed so as to correspond to the magnetoresistive element, and which has a function of being physically deformed at the time of data writing, and of controlling a magnitude of a switching magnetic field of the magnetoresistive element.

Abstract: A high performance MTJ in an MRAM array is disclosed in which the bottom conductor has an amorphous Ta capping layer. A key feature is a surfactant layer comprised of oxygen that is formed on the Ta surface. The resulting smooth and flat Ta capping layer promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-?m2. The MTJ configuraton is extendable to a 0.2×0.4 micron MTJ bit size.

Abstract: A magneto-resistance transistor including a magneto-resistant element which may function as an emitter and a passive element which may function as a collector. The base may be interposed between the passive element and the magneto-resistant element, thereby coupling the passive element with the magneto-resistant element. A magnetic field of a given strength may be applied to at least a portion of the magneto-resistant transistor, the given strength determining a resistance in the at least a portion of the magneto-resistant transistor. Thus, by adjusting the given strength of the magnetic field, the resistance may be adjusted. Therefore, different emitter current inputs may be achieved with a fixed voltage. Further, a base current may vary with a controlled variation of the emitter current input.

Abstract: The present invention is aimed at enabling a spin-transfer magnetization switching in the random access magnetic memory by reducing a switching current density in the spin-transfer magnetization switching to an order smaller than 10 MA/cm2 and without causing breakdowns neither in the memory element which uses a TMR film nor in the element selection FET. The memory layer in the magnetoresistance effect element comprises a magnetic film having a value of saturation magnetization in a range from 400 kA/m to 800 kA/m. The memory layer comprises a magnetic film which contains one or more magnetic elements selected from the group of, for example, cobalt, iron and nickel, and which further contains a non-magnetic element. The non-magnetic element is contained at a ratio of, for example, 5 at % or more and less than 50 at %. A memory layer 12 in the memory cell has a dimension less than 200 nm?.

Abstract: The flash cell includes a silicon substrate; a floating gate formed on a predetermined area of the silicon substrate; a control gate formed on the floating gate and the silicon substrate; a piezoelectric layer formed on the control gate; and an upper electrode formed on the piezoelectric layer. The flash cell brings the control gate in contact with the floating gate, instead of electrically removing electrons contained in the floating gate, resulting in a charge equilibrium state. Therefore, the flash cell completely solves the over-erasing problem. If a voltage signal is applied to the flash cell, the flash cell uses the displacement of piezoelectric/electrostrictive materials. The displacement occurs according to the received voltage, such that the flash cell implements at high speed compared to conventional electric erasing methods.

Abstract: A ultrathin magnetoelectric transducer and its manufacturing method are provided which enable the quality of mounting to be inspected nondestructively, and can reduce a footprint. The magnetoelectric transducer has a substrate composed of a nonmagnetic substrate, and includes bottom surface connecting electrodes whose leads have a first thickness, and side electrodes which are exposed by dicing and have the first thickness. A more sensitive Hall element has a high-permeability magnetic substrate as the substrate, and includes the bottom surface connecting electrodes whose leads have the first thickness, and the side electrodes exposed by the dicing and having the first thickness. The bottom surface connecting electrodes of the leads with the first thickness are formed across the internal electrodes of adjacent magnetoelectric transducers with maintaining the first thickness. The side electrodes with the first thickness are formed by cutting the center between the adjacent magnetoelectric transducers.

Abstract: According to the present invention, a thin film made of a wurtzite structure compound is manufactured by a reactive sputtering using a metal material as a target, and a nitrogen gas or an oxygen gas as a reactive gas. By optimizing film-forming conditions when manufacturing the film, it is possible to obtain a wurtzite thin film whose polarization directions of crystal grains are aligned in a uniform direction. According to a laminate of the present invention, a first wurtzite crystalline layer made of a wurtzite crystalline structure compound is formed in advance between a substrate and a functional material layer that is a ground. Thus, it is possible to improve the crystallinity and crystalline orientation of a second wurtzite crystalline layer formed on the functional material layer.

Abstract: A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. A second set of trenches, perpendicular to the first set, is formed to separate columns of the array. Word lines are formed along rows of the array. The word lines are formed into the second set of trenches in order to shield adjacent floating gates. Metal shields are formed in the first set of trenches along the rows and between floating gates on the pillars.

Abstract: A structure (and method) for a piezoelectric device, including a layer of piezoelectric material. A nanotube structure is mounted such that a change of shape of the piezoelectric material causes a change in a stress in the nanotube structure.

Abstract: A semiconductor sensor production method includes the steps of (A) forming a first etching mask layer on a support part segment of a backside semiconductor layer, except on a portion of the support part segment which portion is along edges of the support part segment; (B) forming a second etching mask layer on the support part segment and a proof mass part segment of the backside semiconductor layer; (C) selectively removing segments of the back side semiconductor layer between the proof mass part segment and the support part segment by performing etching; (D) making the proof mass part segment of the back side semiconductor layer thinner than the support part segment of the back side semiconductor layer by performing etching; and (E) removing the first etching mask layer by using a wet etching method.

Abstract: A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

Abstract: A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.

Abstract: An MTJ MRAM cell is formed above or below an intersection of vertically separated, magnetically clad, ultra-thin orthogonal word and bit lines whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately two for a given current. The word and bit lines also include a soft magnetic layer of high permeability formed on their surfaces distal from the cell to improve the magnetic field still further. The fabrication of a cell with such thin lines is actually simplified as a result of the thinner depositions and eliminates the necessity of removing material by CMP during patterning and polishing, thereby producing uniform spacing between the lines and the cell free layer.

Abstract: A semiconductor memory device includes a memory cell, a side wall insulating film, and an interlayer insulating film. A memory cell includes a first ferromagnetic film, a tunnel barrier film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the tunnel barrier film. The side wall insulating film is formed so as to surround at least sides of the second ferromagnetic film. The interlayer insulating film is formed so as to cover the memory cell and the side wall insulating film.

Abstract: In a manufacturing method for a piezoelectric actuator a first electrode layer is formed on substrate, a ferroelectric thin film is formed on the first electrode layer, and an inorganic protective layer 4 is formed on the ferroelectric thin film. Then, the inorganic protective layer 4 and the ferroelectric thin film are heat-treated under an oxygen containing atmosphere, and a second electrode layer is formed on an oxidation diffusion layer, wherein the oxidation diffusion layer is formed on a surface of the ferroelectric thin film as a result of component diffusion of the ferroelectric thin film and oxidation of the inorganic protective layer 4 due to the heat treatment. By using this method, it is possible to improve ferroelectricity without deterioration or cracking of a surface of the ferroelectric thin film.

Abstract: A data selection line (write line) is disposed right on a MTJ element. Upper and side surfaces of the data selection line are coated with yoke materials which have a high permeability. The yoke materials are separated from each other by a barrier layer. Similarly, a write word line is disposed right under the MTJ element. The lower and side surfaces of the write word line are also coated with the yoke materials which have the high permeability. The yoke materials on the lower and side surfaces of the write word line are also separated from each other by the barrier layer.

Abstract: The present invention provides techniques for data storage. In one aspect of the invention, a semiconductor device is provided. The semiconductor device comprises at least one free layer and at least one fixed layer, with at least one barrier layer therebetween. At least one pinned magnetic layer is separated from the at least one free layer by at least one non-magnetic layer, the at least one pinned magnetic layer and non-magnetic layer being configured to cancel out at least a portion of a Neel coupling between the at least one free layer and the at least one fixed layer.

Abstract: In a spin valve type element, an interface insertion layer (32, 34) of a material exhibiting large spin-dependent interface scattering is inserted in a location of a magnetically pinned layer (16) or a magnetically free layer (20) closer to a nonmagnetic intermediate layer (18). A nonmagnetic back layer (36) may be additionally inserted as an interface not in contact with the nonmagnetic intermediate layer to increase the output by making use of spin-dependent interface scattering along the interface between the pinned layer and the nonmagnetic back layer or between the free layer and the nonmagnetic back layer.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: A magnetic random access memory (MRAM) has multiple stacked memory layers, with each memory layer being a plurality of alternating rows of memory cells and electrically conductive access lines. The access lines in each layer are aligned with the access lines in the layers above and below. Similarly the memory cell rows in each layer are aligned with the memory cell rows in the layers above and below, with the memory cells in adjacent layers forming memory cell columns that extending perpendicularly from the MRAM substrate. The memory cells are connected to bit and word lines for addressing selected cells. The MRAM includes electrical circuitry connected to the access lines for directing currents through the access lines in the memory layer of the selected cell and in the access lines directly above or below to generate magnetic fields that switch the magnetic state of the selected cell without switching the magnetic state of non-selected cells in the memory layers above and below.

Abstract: Magnetic random access memory including a cell array stacked in a plurality of plane levels, a plurality of write wirings disposed on each of the stacked cell array, and a contact plug commonly or independently coupled to the plurality of stacked array planes. Also, a method for manufacturing magnetic random access memory so as to reduce influences of parasitic wiring resistances due to differences of the writing current values for supplying the stacked cell array. The magnetic random access memory includes a cell array of TMR elements stacked in a plurality of plane levels, a plurality of write wirings being formed so that a parasitic resistance becomes smaller accompanying a longer distance from a drive current source, and one or a plurality of contact plugs for commonly or independently coupling to the plurality of stacked array planes.

Abstract: A surface acoustic wave device includes a SAW having an IDT disposed on a piezoelectric substrate, a conductive pad connected to the IDT, and a bonding substrate, wherein the SAW is bonded to the bonding substrate such that a protective space of the IDT is provided. The bonding substrate includes a through-hole in which an external terminal connection member connected to the conductive pad and an external terminal are disposed. The SAW is bonded to the bonding substrate by an adhesive layer including a solder layer.

Abstract: An HGA dynamics tester and method are provided in which a shear mode piezo actuator having a dimensional change responsive to an input voltage while supported on a mass is coupled through an HGA support to impart movement to the HGA responsive to the actuator dimensional change.

Abstract: An MRAM array is formed of MTJ cells shaped so as to have their narrowest dimension at the middle of the cell. A preferred embodiment forms the cell into the shape of a kidney or a peanut. Such a shape provides each cell with an artificial nucleation site at the narrowest dimension, where an applied switching field can switch the magnetization of the cell in manner that is both efficient and uniform manner across the array.

Abstract: The present invention provides a magnetic memory device capable of performing stable operation efficiently using a magnetic field generated by write current and formed with high precision while realizing a compact configuration. Since a plating film is used for at least a part of a magnetic yoke, as compared with the case of formation by a dry film forming method, sufficient thickness and higher dimensional precision can be obtained. Consequently, a more stabilized return magnetic field can be generated and high reliability can be assured. Neighboring memory cells can be disposed at narrower intervals, so that the invention is suitable for realizing higher integration and higher packing density.

Abstract: The present invention discloses an MRAM wherein a write word line is disposed between every other set of the word lines and a ground line is disposed between every other bit lines. This structure of MRAM in accordance with the present invention, Which is similar to folded bit line DRAM having a unit cell area of 8F2, allows read and write operation of MRAM with reduced number of required lines.

Abstract: A magnetic random access memory device including a pinned layer having a diffusion barrier, a sense layer, and a tunnel barrier to electrically couple the pinned layer to the sense layer. A method for forming a magnetic random access memory device including forming, on a substrate, a sense layer, forming a tunnel barrier on the sense layer, forming a pinned layer on the tunnel barrier, where the pinned layer includes a diffusion barrier to stop manganese atoms from diffusing to the interface of the tunnel barrier, and annealing the substrate, the sense layer, the tunnel barrier and the pinned layer. The diffusion barrier can include a native oxide having a thickness up to about seven angstroms or an aluminum oxide having a thickness up to about seven angstroms.

Abstract: A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

Abstract: A multilayered conductive memory device capable of storing information individually or as part of an array of memory devices is provided. Boundary control issues at the interface between layers of the device due to the use of incompatible materials can be avoided by intentionally doping the conductive metal oxide layers that are comprised of substantially similar materials. Methods of manufacture are also provided herein.

Abstract: A magnetic random access memory (MRAM) including an array of magnetic memory cells and a plurality of word and bit lines connecting columns and rows of the memory cells. Each memory cell has a magnetic reference layer and a magnetic data layer. Each reference layer and each data layer has a magnetization that is switchable between two states under the influence of a magnetic field. The MRAM also includes a plurality of heating elements each proximate to a respective reference layer. Each heating element provides in use for localized heating of the respective reference layer so as to reduce the coercivity of the reference layer to facilitate switching of the reference layer without switching of the data layers.