Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus, distribution and magnitude of a desired stress can be secured for a channel region of a MOSFET in a mounted chip even after performance of the package manufacturing process. As a result, a mobility is increased and current driving power is enhanced.

Abstract: An electric energy generator may include a semiconductor layer and a plurality of nanowires having piezoelectric characteristics. The electric energy generator may convert optical energy into electric energy if external light is applied and may generate piezoelectric energy if external pressure (e.g., sound or vibration) is applied.

Abstract: An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the changed defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons.

Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.

Abstract: Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.

Abstract: A sensor for acoustic applications such as a silicone microphone is provided containing a backplate provided with apertures and a flexible diaphragm formed from a silicon on insulator (SOI) wafer which includes a layer of heavily doped silicon, a layer of silicon and an intermediate oxide layer that is connected to, and insulated from the backplate. The arrangement of the diaphragm in relation to the rest of the sensor and the sensor location, being mounted over the aperture in a PCB, reduces the acoustic signal pathway which allows the sensor to be both thinner and more importantly, enables there to be a greater back volume.

Abstract: A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROMB) is disclosed. It can achieve large bit-per-cell (e.g. 4-bpc or more). 3D-MPROMB can be realized by adding resistive layer(s) or resistive element(s) to the memory cells.

Abstract: A system and method of manufacturing and using a magnetic tunnel junction device is disclosed. In a particular embodiment, a magnetic tunnel junction device includes a first free layer and second free layer. The magnetic tunnel junction also includes a spin torque enhancement layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers that includes a material and has a thickness that substantially inhibits exchange coupling between the first and second free layers. The first and second free layers are magneto-statically coupled.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.

Abstract: The present invention relates a method of fabricating a piezoelectric device through micromachining piezoelectric-on-silicon wafer. The wafers are constructed so that piezoelectric layer is a single wafer having a thin layer from 5 to 50 ?m.

Abstract: A reliable long life RF-MEMS capacitive switch is provided with a dielectric layer comprising a “fast discharge diamond dielectric layer” and enabling rapid switch recovery, dielectric layer charging and discharging that is efficient and effective to enable RF-MEMS switch operation to greater than or equal to 100 billion cycles.

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract: Nonvolatile resistive memory devices are disclosed. In some embodiments, the memory devices comprise multilayer structures including electrodes, one or more resistive storage layers, and separation layers. The separation layers insulate the resistive storage layers to prevent charge leakage from the storage layers and allow for the use of thin resistive storage layers. In some embodiments, the nonvolatile resistive memory device includes a metallic multilayer comprising two metallic layers about an interlayer. A dopant at an interface of the interlayer and metallic layers can provide a switchable electric field within the multilayer.

Abstract: A device comprising a diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and the diblock copolymer mask, the diblock copolymer mask comprising a first plurality of uniform shapes formed on and registered to the template.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

Abstract: Methods of forming electro-micromechanical resonators provide passive temperature compensation of semiconductor device layers used therein. A first substrate is provided that includes a first electrically insulating temperature compensation layer on a first semiconductor device layer. A step is performed to bond the first electrically insulating temperature compensation layer to a second substrate containing the second electrically insulating temperature compensation layer therein, to thereby form a relatively thick temperature compensation layer. A piezoelectric layer is formed on the first electrically insulating temperature compensation layer and at least a first electrode is formed on the piezoelectric layer.

Abstract: An integrated MEMS device is provided, including, from bottom up, a bonding wafer layer, a bonding layer, an aluminum layer, a CMOS substrate layer defining a large back chamber area (LBCA), a small back chamber area (SBCA) and a sound damping path (SDP), a set of CMOS wells, a field oxide (FOX) layer, a set of CMOS transistor sources/drains, a first polysilicon layer forming CMOS transistor gates, a second polysilicon layer, said CMOS wells, said CMOS transistor sources/drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with a plurality of metal layers interleaved with a plurality of via hole layers, and a gap control layer, an oxide layer, a first Nitride deposition layer, a metal deposition layer, a second Nitride deposition layer, an under bump metal (UBM) layer made of preferably Al/NiV/Cu and a plurality of solder spheres.

Abstract: A resistor with improved switchable resistance includes a first electrode, a second electrode, and an insulating dielectric structure between the first and second electrodes. The insulating dielectric structure includes a confined conductive region providing a first resistance state and a second resistance state; the resistance state of the confined conductive region being switchable between the first and second resistance states by a control signal.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed to one side of the MTJ. The induction line is configured to induce a perpendicular magnetic field at the MTJ.

Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.

Abstract: A semiconductor-centered MEMS device (100) integrates the movable microelectromechanical parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, and leaving only the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package is substrate-based and has an opening through the thickness of the substrate. Substrate materials include polymer tapes with attached metal foil, and polymer-based and ceramic-based multi-metal-layer dielectric composites with attached metal foil. The movable part is formed from the metal foil attached to a substrate surface and extends at least partially across the opening. The chip is flip-assembled to span at least partially across the membrane, and is separated from the membrane by a gap.

Abstract: A composite free layer having a FL1/insertion/FL2 configuration is disclosed for achieving high dR/R, low RA, and low ? in TMR or GMR sensors. Ferromagnetic FL1 and FL2 layers have (+) ? and (?) ? values, respectively. FL1 may be CoFe, CoFeB, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, or Nb. FL2 may be CoFe, NiFe, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, Nb, or B. The thin insertion layer includes at least one magnetic element such as Co, Fe, and Ni, and at least one non-magnetic element selected from Ta, Ti, W, Zr, Hf, Nb, Mo, V, Cr, or B. In a TMR stack with a MgO tunnel barrier, dR/R>60%, ?˜1×10?6, and RA=1.2 ohm-um2 when FL1 is CoFe/CoFeB/CoFe, FL2 is CoFe/NiFe/CoFe, and the insertion layer is CoTa or CoFeBTa.

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the micro electromechanical systems device.

Abstract: A lid for a MEMS device and the relative manufacturing method. The lid includes: a first board with opposite first and second surfaces having first and second metal layers disposed thereon, respectively, wherein a through cavity extends through the first board and the first and second metal layers; a second board with opposite third and fourth surfaces; an adhesive layer sandwiched between the second surface of the first board and the third surface of the second board to couple the first and second boards together such that the through cavity is closed by the second board, thereby forming a recess; and a first conductor layer coating the bottom and the side surfaces of the recess.

Abstract: An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.

Abstract: Some embodiments provide force input control devices for sensing vector forces comprising: a sensor die comprising: a rigid island, an elastic element coupled to the rigid island, die frame coupled to a periphery of the elastic element, one or more stress sensitive components on the elastic element, and signal processing IC, where the sensor die is sensitive to a magnitude and a direction of a force applied to the rigid island within the sensor die, where the sensor die is coupled electrically and mechanically to a substrate, a spring element coupling an external button, where the force is applied, to the rigid island element, wherein the spring element has a flat geometry and located in a plane parallel to a plane of the substrate, where the spring element is configured to translate a deflection of the button into an allowable force applied to the rigid island.

Abstract: A method of bonding a semiconductor substrate having a substrate 11 formed with a MEMS sensor and a substrate 21 having a bonding portion 30b film-formed by contacting an aluminum containing layer 31 with a germanium layer 32 on either a front surface or a rear surface and formed with an integrated circuit that controls the MEMS sensor, either a front surface or a rear surface of the substrate 11 is put to contact directly on the bonding portion of the substrate 21 to bond by eutectic bonding with pressurization and heating.

Abstract: Methods for making a programmable metallization memory cell are disclosed.

Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

Abstract: A dynamic quantity sensor device includes: first and second dynamic quantity sensors having first and second dynamic quantity detecting units; and first and second substrates, which are bonded to each other to provide first and second spaces. The first and second units are air-tightly accommodated in the first and second spaces, respectively. A SOI layer of the first substrate is divided into multiple semiconductor regions by trenches. First and second parts of the semiconductor regions provide the first and second units, respectively. The second part includes: a second movable semiconductor region having a second movable electrode, which is provided by a sacrifice etching of the embedded oxide film; and a second fixed semiconductor region having a second fixed electrode. The second sensor detects the second dynamic quantity by measuring a capacitance between the second movable and fixed electrodes, which is changeable in accordance with the second dynamic quantity.

Abstract: A piezoresistive pressure sensor is provided, which can prevent the occurrence of ESD breakdown due to the nearness of interconnection layers of a resistive element according to miniaturization thereof. The piezoresistive pressure sensor is so configured that respective semiconductor resistive layers on both sides of an arrangement are formed to be relatively longer than an adjacent semiconductor resistive layer, and thus a corner portion of a semiconductor connection layer that extends from the respective semiconductor resistive layers on both sides of the arrangement and a corner portion of the semiconductor interconnection layer that is nearest to the corner portion of the semiconductor connection layer, between which the ESD breakdown occurs easily, can be separated from each other.

Abstract: The invention relates to the preparation of multilayer microcomponents which comprise one or more films, each consisting of a material M selected from metals, metal alloys, glasses, ceramics and glass-ceramics. The method consists in depositing on a substrate one or more films of an ink P, and one or more films of an ink M, each film being deposited in a predefined pattern selected according to the structure of the microcomponent, each film of ink P and each film of ink M being at least partially consolidated before deposition of the next film; effecting a total consolidation of the films of ink M partially consolidated after their deposition, to convert them to films of material M; totally or partially removing the material of each of the films of ink P. An ink P consists of a thermoset resin containing a mineral filler or a mixture comprising a mineral filler and an organic binder. An ink M consists of a mineral material precursor of the material M and an organic binder.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: A reliable long life RF-MEMS capacitive switch is provided with a dielectric layer comprising a “fast discharge diamond dielectric layer” and enabling rapid switch recovery, dielectric layer charging and discharging that is efficient and effective to enable RF-MEMS switch operation to greater than or equal to 100 billion cycles.

Abstract: An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.

Abstract: Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.

Abstract: The invention relates to a spin current thermal conversion device and a thermoelectric conversion device, with which a spin current is thermally generated, and its concrete application is realized. A temperature gradient creating means which creates a temperature gradient in a thermal spin current generating member is provided in a thermal spin current generating member made of either a ferromagnetic member or a conductive member containing a ferromagnetic substance.

Abstract: There are disclosed an epitaxial film, comprising: heating an Si substrate provided with an SiO2 layer with a film thickness of 1.0 nm or more to 10 nm or less on a surface of the substrate; and forming on the SiO2 layer by use of a metal target represented by the following composition formula: yA(1?y)B??(1), in which A is one or more elements selected from the group consisting of rare earth elements including Y and Sc, B is Zr, and y is a numeric value of 0.03 or more to 0.20 or less, the epitaxial film represented by the following composition formula: xA2O3?(1?x)BO2??(2), in which A and B are respectively same elements as A and B of the composition formula (1), and x is a numeric value of 0.010 or more to 0.035 or less.

Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.

Abstract: A device comprises a first means for separating a conductive layer from a semiconductor substrate and a second means for reducing a voltage dependent capacitive coupling between the conductive layer and the semiconductor substrate.

Abstract: This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one integrated nano-contact intended to inject the current into the magneto-resistive stack. The nano-contact is made in a bilayer composed of a solid electrolyte on which has been deposited a soluble electrode composed of a metal that has been at least partially dissolved in the electrolyte.

Abstract: A test assembly for a disk drive suspension head gimbal assembly includes a steel mount plate and a mount sub-plate of a material such as silicon carbide having a modulus of elasticity to density ratio that is significantly higher than the ratio for stainless steel. Preferably the mount plate and the mount sub-plate taken together have a first resonant shear frequency of greater than 50 KHz, which is generally greater than the frequency range of interest for testing head gimbal assemblies. The high modulus of elasticity to density ratio helps to ensure that any shear mode resonances of the test assembly occur at frequencies that are higher than the frequencies of interesting for head gimbal assembly shear resonance testing purposes.

Abstract: A resistor with improved switchable resistance and a non-volatile memory device includes a first electrode, a second electrode facing the first electrode and a resistance structure between the first electrode and the second electrode. The resistance structure includes an insulating dielectric material in which a confined switchable conductive region is formed between the first and second electrode. The resistor further includes a perturbation element, locally exerting mechanical stress on the resistance structure in the vicinity of the perturbation element at least during a forming process in which the confined switchable conductive region is formed.

Abstract: A tuning fork vibration device includes: a SOI substrate having a substrate, an oxide layer formed above the substrate and a semiconductor layer formed above the oxide layer; a tuning fork type vibration section that is formed by processing the semiconductor layer and the oxide layer and composed of the semiconductor layer; and a driving section for generating flexural vibration of the vibration section, wherein the vibration section includes a support section and two beam sections formed in a cantilever shape with the support section as a base of the beam sections, and the driving section includes a pair of drivers formed on each of the two beam sections, each of the drivers including a first electrode layer, a piezoelectric layer formed above the first electrode layer and a second electrode layer formed above the piezoelectric layer.