Abstract: A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.

Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element.

Abstract: A first electrode is formed on a semiconductor substrate. A second electrode is formed separately at a predetermined interval from the first electrode, and has at least one opening. An actuator layer is connected to the second electrode, and drives the second electrode.

Abstract: A magnetic random access memory of an aspect of the present invention including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed and recording layers, wherein the magnetization directions of the fixed and recording layers are in a parallel state or in an anti-parallel state depending on a direction of a current flowing between the fixed and recording layers, a first transistor having a gate and a first current path having one end connected to the fixed layer, a second transistor having a gate and a second current path having one end connected to the recording layer, a first bit line to which other end of the first current path is connected, and a second bit line to which other end of the second current path is connected.

Abstract: Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD) material (106, 108, 110, 158, 160, 162, 458, 460, 462) disposed adjacent the magnetoelectronic device. The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprises multiple composite layers (408) of magnetic nano-particles (406) embedded in a dielectric matrix (409). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device (102, 152, 452) and depositing the programming line (104, 154, 156, 454, 456).

Abstract: The present invention provides a low resistance high magnetoresistance (MR) device comprised of a junction of two magnetic elements separated by a magnesium oxide (MgO) layer doped with such metals as Al and Li. Such device can be used as a sensor of magnetic field in magnetic recording or as a storage element in magnetic random access memory (MRAM). The invention provides a high-MR device possessing a diode function, comprised of a double junction of two outer magnetic elements separated by two MgO insulating layer and a center MgO layer doped with such metals as Al and Li. Such device provides design advantages when used as a storage element in MRAM. The invention with MR wherein a gate electrode is placed in electrical or physical contact to the center layer of the double tunnel junction.

Abstract: A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0?Ms<?{square root over ( )}{Jw/(6?At)}. Jw is a write current density, t is a thickness of the free layer, A is a constant.

Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.

Abstract: A semiconductor device using a MEMS technology according to an example of the present invention comprises a cavity, a lower electrode provided in a lower part of the cavity, an actuator provided in an upper part or inside of the cavity, an upper electrode connected to the actuator, and a conductive layer in contact with the lower electrode outside the cavity via a contact hole whose bottom face is provided above an upper face of the lower electrode in the cavity.

Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.

Abstract: Improved SAW pressure sensors and manufacturing methods thereof. A SAW wafer including a number of SAW transducers disposed thereon may be provided. A cover wafer may also be provided, with a glass wall situated between the cover wafer and the SAW wafer. The cover wafer may be secured to the SAW wafer such that the glass wall surrounds the SAW transducers. In some instances, the glass wall may define, at least in part, a separation between the cover wafer and the SAW wafer. One or more contours may also be provided between the cover wafer and the SAW wafer such that at least one of the contours surrounds at least one of the SAW transducers when the cover wafer is disposed over and secured relative to the SAW wafer.

Abstract: Microelectromechanical systems with structures having piezoelectric actuators are described. The structures each have a body that supports piezoelectric islands. The piezoelectric islands have a first surface and a second opposite surface. The piezoelectric islands can be formed, in part, by forming cuts into a thick layer of piezoelectric material, attaching the cut piezoelectric layer to a body having etched features and grinding the piezoelectric layer to a thickness that is less than the depths of the cuts. Conductive material can be formed on the piezoelectric layer to form electrodes.

Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.

Abstract: A magnetic random access memory (MRAM) device includes a reference magnetic region having a resultant magnetic moment vector generally maintained in a desired orientation without the use of exchange coupling thereto. A storage magnetic region has an anisotropy easy axis and a resultant magnetic moment vector oriented in a position parallel or antiparallel to that of the reference magnetic region. A tunnel barrier is disposed between the reference magnetic region and the storage magnetic region, with the reference magnetic region, storage magnetic region and tunnel barrier defining a storage cell configured for a toggle mode write operation. The storage cell has an offset field applied thereto so as to generally maintain the resultant magnetic moment vector of the reference magnetic region in the desired orientation.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: A pressure sensor includes a base substrate silicon fusion bonded to a cap substrate with a chamber disposed between the base substrate and the cap substrate. Each of the base substrate and the cap substrate include silicon. The base substrate includes walls defining a cavity and a diaphragm portion positioned over the cavity, wherein the cavity is open to an environment to be sensed. The chamber is hermetically sealed from the environment.

Abstract: A spin-transfer MRAM bit includes a free magnet layer positioned between a pair of spin polarizers, wherein at least one of the spin polarizers comprises an unpinned synthetic antiferromagnet (SAF). The SAF may include two antiparallel fixed magnet layers separated by a coupling layer. To improve manufacturability, the layers of the SAF may be non-symmetrical (e.g., having different thicknesses or different inherent anisotropies) to assist in achieving proper alignment during anneal. The total magnetic moment of the SAF may be greater than that of the free magnet layer.

Abstract: A preferred embodiment of the invention provides a semiconductor device. A preferred device comprises an n-channel transistor and a p-channel transistor disposed in a semiconductor body and a piezoelectric layer overlying the n-channel transistor and the p-channel transistor. In a preferred embodiment of the invention, the piezoelectric layer is biased to a first potential at a portion near the n-channel transistor and is biased to a second potential as a portion near the p-channel transistor.

Abstract: A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Improved methods, and related systems and devices, for fabricating selectively patterned piezoelectric substrates suitable for use in a wide variety of systems and devices. A method can include providing a piezoelectric substrate having a protrusion of substrate material, depositing an electrically conductive coating so as to cover a portion of a side of the substrate and protrusion, and removing a portion of the coated protrusion.

Abstract: A semiconductor device using a MEMS technology according to an example of the present invention comprises a cavity, a lower electrode positioned below the cavity, a moving part positioned in the cavity, an upper electrode coupled with the moving part, a film which covers an upper part of the cavity and has an opening, and a material which closes the opening and seals the cavity.

Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.

Abstract: Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration of arrays of quartz devices of different frequencies with the same electronics.

Abstract: MEMS piezoelectric switches 100 that provide advantages of compact structure ease of fabrication in a single unit, and that are free of high temperature-induced morphological changes of the contact materials and resultant adverse effects on properties. High temperature-induced morphological changes refer to changes that occur during fabrication when metallic contacts such as radio frequency lines 125, 130 and shorting bars 150 are exposed to temperatures required to anneal a piezoelectric layer or those temperatures encountered during high temperature deposition of the piezoelectric layer, if such process is used instead.

Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.

Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Abstract: A method for producing a sensor array including a monolithically integrated circuit is described as well as a sensor array. This sensor array has a micromechanical sensor structure, in which a first partial structure which is associated with the sensor structure is produced at the same time as a second partial structure which is associated with the circuit, a process variation of the first partial structure being performed in order to adjust a structure property of the sensor structure while the second partial structure remains the same.

Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

Abstract: Magnetic or magnetoresistive random access memories (MRAMs) are implemented in a variety of arrangements and methods. Using one such arrangement, a matrix is implemented with magnetoresistive memory cells logically organized in rows and columns, each memory cell including a magnetoresistive element. The matrix has a set of column lines, a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column, wherein each column line has a forward column line and a return column line arranged on opposite sides of the magnetoresistive element and offset from one another for forming a return path for current in that column line.

Abstract: A package inner peripheral face 13 of a base 4 is made up of a vertical face 14 and a horizontal face 15, and electrode pads 7 (71 to 78) are formed on the vertical face vertical face 14 of the base 4. The electrode pads 71 to 78 are formed on the vertical face 14 of the base 4 including an intersection line 17 at which the vertical face 14 and the horizontal face 15 intersect; for example, electrode pads 74 and 75 that serve as hetero electrodes are formed adjacently. The distance between the electrode pads 74 and 75 that are adjacent along the intersection line 17 of the vertical face 14 of the base 4 is longer than the shortest distance between the electrode pads 74 and 75 that are adjacent on the vertical face 14 of the base 4.

Abstract: A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A memory element is provided. The memory element includes a memory layer that retains information based on a magnetization state of a magnetic material, in which a magnetization pinned layer is provided for the memory layer through an intermediate layer, the intermediate layer is formed of an insulator, spin-polarized electrons are injected in a stacking direction to change a magnetization direction of the memory layer, so that information is recorded in the memory layer, and a fine oxide is dispersed in an entire or part of a ferromagnetic layer forming the memory layer.

Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever

Abstract: A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: Disclosed is a piezoelectric ink jet printer head in which a chamber and an ink storage are integrally formed. A process for manufacturing the ink jet printer head is also disclosed.

Abstract: A MTJ structure is disclosed in which the seed layer is made of a lower Ta layer, a middle Hf layer, and an upper NiFe or NiFeX layer where X is Co, Cr, or Cu. Optionally, Zr, Cr, HfZr, or HfCr may be employed as the middle layer and materials having FCC structures such as CoFe and Cu may be used as the upper layer. As a result, the overlying layers in a TMR sensor will be smoother and less pin dispersion is observed. The Hex/Hc ratio is increased relative to that for a MTJ having a conventional Ta/Ru seed layer configuration. The trilayer seed configuration is especially effective when an IrMn AFM layer is grown thereon and thereby reduces Hin between the overlying pinned layer and free layer. Ni content in the NiFe or NiFeX middle layer is above 30 atomic % and preferably >80 atomic %.

Abstract: A semiconductor device according to an embodiment includes an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain, a first contact wiring line which is provided on the source, a second contact wiring line which is provided on the drain, and a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines.

Abstract: In a spin valve type element, an interface insertion layer (32, 34) of a material exhibiting large spin-dependent interface scattering is inserted in a location of a magnetically pinned layer (16) or a magnetically free layer (20) closer to a nonmagnetic intermediate layer (18). A nonmagnetic back layer (36) may be additionally inserted as an interface not in contact with the nonmagnetic intermediate layer to increase the output by making use of spin-dependent interface scattering along the interface between the pinned layer and the nonmagnetic back layer or between the free layer and the nonmagnetic back layer.

Abstract: A magnetic recording element according to an example of the present invention includes a magnetic free layer whose magnetization is variable in accordance with a current direction passing through a film and whose direction of easy axis of magnetization is a direction perpendicular to a film plane, a magnetic pinned layer whose magnetization is fixed to a direction perpendicular to the film plane, and a non-magnetic barrier layer between the magnetic free layer and the magnetic pinned layer. In the magnetic free layer, a relation between a saturated magnetization Ms (emu/cc) and an anisotropy field Han (Oe) satisfies Han>12.57 Ms, and Han<1.2 E7 Ms?1+12.57 Ms.

Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.

Abstract: A semiconductor device includes a resistor element formed in a semiconductor layer of an SOI substrate (Silicon On Insulator). The semiconductor device includes a low concentration impurity area formed in the semiconductor layer as the resistor element; a high concentration impurity area formed in the semiconductor layer as a resistor element wiring portion; and a silicide layer selectively formed on the high concentration impurity area. The high concentration impurity area includes one end portion contacting with an end portion of the low concentration impurity area, and the other end portion contacting with an impurity area of another element.

Abstract: A MEMS pixel sensor is provided with a thin-film mechanical device having a mechanical body, with a mechanical state responsive to a proximate environment. A thin-film electronic device converts the mechanical state into electrical signals. A pixel interface supplies power to the electronic device and transceives electrical signals. The sensor is able to operate dynamically, in real-time. For example, if the mechanical device undergoes a sequence of mechanical states at a corresponding plurality of times, the electronic device is able to supply a sequence of electrical signals to the pixel interface that are responsive to the sequence of mechanical states, at the plurality of times. Each MEMS pixel sensor may include a number of mechanical devices, and corresponding electronic devices, to provide redundancy or to measure a broadband response range.

Abstract: A giant magnetoresistive memory device includes a magnetic sense layer, a magnetic storage layer, a non-magnetic spacer layer between the magnetic sense layer and the magnetic storage layer, and an antiferromagnetic layer formed in proximity to the magnetic storage layer. The antiferromagnetic layer couples magnetically in a controlled manner to the magnetic storage layer such that the magnetic storage layer has uniform and/or directional magnetization. Additionally or alternatively, an antiferromagnetic layer may be formed in proximity to the magnetic sense layer. The antiferromagnetic layer in proximity to the magnetic sense layer couples magnetically in a controlled manner to the magnetic sense layer such that the magnetic sense layer has uniform and/or directional magnetization.

Abstract: A magnetic memory device includes a first interconnection which runs in a first direction, a second interconnection which runs in a second direction different from the first direction, a magnetoresistive element which is arranged at the intersection of and between the first and second interconnections, and a metal layer which is connected to the magnetoresistive element and has a side surface that partially coincides with a side surface of the magnetoresistive element.

Abstract: A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.