Abstract: According to an embodiment of the present invention, a MEMS apparatus includes a plurality of recesses opened to a surface, a substrate having an insulator, an air gap, or an insulator and an air gap formed in the recesses, an insulating layer formed on the substrate, and a MEMS device having a signal line formed on the insulating layer, wherein the position of the signal line in a direction parallel to the surface of the substrate overlaps the position of the recess in the direction.

Abstract: A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.

Abstract: A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio of the second length to the first length is a first value. The second magnetoresistive effect element is used to determine a resistance state of the first magnetoresistive effect element. A shape of the second magnetoresistive effect element has a third length in a third direction and a fourth length in a fourth direction. The fourth length is equal to or greater than the third length. A ratio of the fourth length to the third length is a second value which is greater than the first value.

Abstract: Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.

Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Abstract: A composite free layer having a FL1/insertion/FL2 configuration is disclosed for achieving high dR/R, low RA, and low ? in TMR or GMR sensors. Ferromagnetic FL1 and FL2 layers have (+) ? and (?) ? values, respectively. FL1 may be CoFe, CoFeB, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, or Nb. FL2 may be CoFe, NiFe, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, Nb, or B. The thin insertion layer includes at least one magnetic element such as Co, Fe, and Ni, and at least one non-magnetic element selected from Ta, Ti, W, Zr, Hf, Nb, Mo, V, Cr, or B. In a TMR stack with a MgO tunnel barrier, dR/R>60%, ?˜1×10?6, and RA=1.2 ohm-um2 when FL1 is CoFe/CoFeB/CoFe, FL2 is CoFe/NiFe/CoFe, and the insertion layer is CoTa or CoFeBTa.

Abstract: A finger sensing device may include a mounting substrate, an integrated circuit (IC) die carried by the mounting substrate and having an array of electric field-based finger sensing elements, and first electrical connections coupling the mounting substrate and the IC die. In addition, the finger sensing device may include a protective plate attached over the array of electric field-based finger sensing elements and having a dielectric constant greater than 5 in all directions and a thickness greater than 40 microns to define a capacitive lens for the array of electric field-based finger sensing elements. The finger sensing device may also include an encapsulating material adjacent the mounting substrate and the IC die and around at least the first electrical connections.

Abstract: A semiconducting device includes a substrate, a piezoelectric wire, a structure, a first electrode and a second electrode. The piezoelectric wire has a first end and an opposite second end and is disposed on the substrate. The structure causes the piezoelectric wire to bend in a predetermined manner between the first end and the second end so that the piezoelectric wire enters a first semiconducting state. The first electrode is coupled to the first end and the second electrode is coupled to the second end so that when the piezoelectric wire is in the first semiconducting state, an electrical characteristic will be exhibited between the first electrode and the second electrode.

Abstract: A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0?Ms<?{square root over ( )}{Jw/(6?At)}. Jw is a write current density, t is a thickness of the free layer, A is a constant.

Abstract: A monolithic micro or nano electromechanical transducer device includes a pair of substrates (20, 25) respectively mounting one or more elongate electrical conductors (40) and resilient solid state hinge means (30, 32) integral with and linking the substrates to relatively locate the substrates so that respective elongate electrical conductors (40) of the substrates are opposed at a spacing that permits a detectable quantum tunnelling current between the conductors when a suitable electrical potential difference is applied across the conductors. The solid state hinge means permits relative parallel translation of the substrates transverse to the elongate electrical conductors.

Abstract: A semiconductor device includes: a substrate having a first surface; an insulation layer; a semiconductor layer disposed to the first surface of the substrate with the insulation layer interposed between the semiconductor layer and the first surface; and a piezoelectric layer that is positioned between the first surface and the semiconductor layer, and disposed in a region included and interposed in the insulation layer.

Abstract: An electric power generator includes a first conductive layer, a plurality of semiconducting piezoelectric nanostructures, a second conductive layer and a plurality of conductive nanostructures. The first conductive layer has a first surface from which the semiconducting piezoelectric nanostructures extend. The second conductive layer has a second surface and is parallel to the first conductive layer so that the second surface faces the first surface of the first conductive layer. The conductive nanostructures depend downwardly therefrom.

Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.

Abstract: A method for fabricating a sensor is disclosed that in one embodiment bonds a first device wafer to an etched second device wafer to create a suspended structure, the flexure of which is determined by an embedded sensing element that is in electrical communication with an outer surface of the sensor through an interconnect embedded in a device layer of the first device wafer. In one embodiment the suspended structure is enclosed by a cap and the sensor is configured to measure absolute pressure.

Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.

Abstract: The free layer in a magneto-resistive memory element is stabilized through being pinned by an antiferromagnetic layer. A control valve layer provides exchange coupling between this antiferromagnetic layer and the free layer. When writing data into the free layer, the control valve layer is heated above its curie point thereby temporarily uncoupling the free layer from said antiferromagnetic layer. Once the control valve cools, the free layer magnetization is once again pinned by the antiferromagnetic layer.

Abstract: A magneto-optical structure is provided. The magneto-optical structure includes a substrate. A waveguide layer is formed on the substrate for guiding electromagnetic radiation received by the magneto-optical structure. The waveguide layer includes magnetic oxide material that comprises ABO3 perovskite doped with transition metal ions on the B site, or transition metal ions doped SnO2, or transition metal ions doped CeO2.

Abstract: One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element.

Abstract: An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.

Abstract: A magnetic random access memory of an aspect of the present invention including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed and recording layers, wherein the magnetization directions of the fixed and recording layers are in a parallel state or in an anti-parallel state depending on a direction of a current flowing between the fixed and recording layers, a first transistor having a gate and a first current path having one end connected to the fixed layer, a second transistor having a gate and a second current path having one end connected to the recording layer, a first bit line to which other end of the first current path is connected, and a second bit line to which other end of the second current path is connected.

Abstract: A method of mounting a first integrated circuit (102, 500, 704) on one of a circuit board (300, 700) or a second integrated circuit (706), the first integrated circuit (102, 500, 704) formed over a substrate (104) and having a surface (119) opposed to the substrate (104) and a side (122, 530, 930) substantially orthogonal to the surface (119), and including a conductive element (116, 117, 118, 522, 524, 526, 528, 528?, 528?) coupled to circuitry (102, 500, 704) and formed within a dielectric material (120, 518), the one of the circuit board (300, 700) or the second integrated circuit (706) including a contact point (304, 306, 314), the method including singulating (1104) the first integrated circuit (102, 500, 704) to expose the conductive element (116, 117, 118, 522, 524, 526, 528, 528?, 528?) on the side (222, 630, 1030), and mounting (1108) the first integrated circuit (102, 500, 704) on the one of a circuit board (300, 700) or a second integrated circuit (706) by aligning the conductive element (116, 117,

Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.

Abstract: A system and method of manufacturing and using a magnetic tunnel junction device is disclosed. In a particular embodiment, a magnetic tunnel junction device includes a first free layer and second free layer. The magnetic tunnel junction also includes a spin torque enhancement layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers that includes a material and has a thickness that substantially inhibits exchange coupling between the first and second free layers. The first and second free layers are magneto-statically coupled.

Abstract: A semiconductor is disclosed. In one embodiment, the semiconductor includes a semiconductor substrate having an active area region, a covering configured to protect the active area region, and a carrier. An interspace is located between the carrier and the covering. The interspace is filled with an underfiller material is disclosed.

Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.

Abstract: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R is disclosed. The MTJ has a MgO tunnel barrier formed by natural oxidation to achieve a low RA, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0. There is a thin Ru capping layer for a spin scattering effect. The reference layer has a shape anisotropy and Hc substantially greater than that of the free layer to establish a “self-pinned” state. The free layer, capping layer and hard mask are formed in an upper section of a nanopillar that has an area substantially less than a lower pedestal section which includes a bottom electrode, reference layer, seed layer, and tunnel barrier layer. The reference layer is comprised of an enhanced damping constant material that may be an insertion layer, and the free layer has a low damping constant.

Abstract: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

Abstract: A semiconductor device includes a semiconductor substrate; a gate electrode formed on the semiconductor substrate; source and drain extension regions formed in the semiconductor substrate on a first and a second side corresponding to a first sidewall surface and a second sidewall surface, respectively, of the gate electrode; a first piezoelectric material pattern formed on the semiconductor substrate continuously covering the first sidewall surface of the gate electrode from the first side of the gate electrode; a second piezoelectric material pattern formed on the semiconductor substrate continuously covering the second sidewall surface of the gate electrode from the second side of the gate electrode; and source and drain regions formed in the semiconductor substrate outside the source extension region and the drain extension, respectively.

Abstract: An ultrasonic monitoring system is formed with a probe unit. In one example an array of transducer cells is arranged in rows and columns formed along a first plane with a first pitch along a first direction. An integrated circuit including an array of circuit cells is formed along a second plane parallel to the first plane. The circuit cells are spaced apart along the first direction at a second pitch smaller than the first pitch. A first of the transducer cells is vertically aligned, along a direction normal to one of the planes, with a first of the circuit cells and having a connection thereto. A second of the transducer cells is offset from vertical alignment with respect to the position of a second circuit cell so as to not overlie the second circuit cell.

Abstract: A semiconductor device using a magnetic domain wall movement and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a magnetic layer that is formed on a substrate and has a plurality of magnetic domains, and a unit that supplies energy to move a magnetic domain wall in the magnetic layer. The magnetic layer is formed parallel to the substrate, and includes a plurality of prominences and a plurality of depressions alternately formed along a lengthwise direction thereof. The magnetic layer has a stepped form that secures a reliable movement of the magnetic domain wall in units of one bit.

Abstract: A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.

Abstract: An impact sensor comprises a silicon substrate; an insulating layer formed over the silicon substrate; a plurality of beams having flexibility that are formed of conductive silicon material; a fixing portion to fix a fixed end of each of the beams, the fixing portion being formed of conductive silicon material; a fixed end line at whose one end is formed the fixing portion, the fixed end line being formed of conductive silicon material on the insulating layer; and a free end line having a pressing portion that faces a free end of each of the beams via a space, the free end line being formed of conductive silicon material on the insulating layer. Respective beam widths, each measured in a direction orthogonal to a length direction joining the fixed end and the free end, of the plurality of beams are set different from each other, thus reducing the space occupied by the sensor.

Abstract: Methods are presented for fabricating an MTJ element having a precisely controlled spacing between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not thinned and serves to maintain an exact spacing between the bit line and the MTJ free layer.

Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.

Abstract: A method for producing a sensor array including a monolithically integrated circuit is described as well as a sensor array. This sensor array has a micromechanical sensor structure, in which a first partial structure which is associated with the sensor structure is produced at the same time as a second partial structure which is associated with the circuit, a process variation of the first partial structure being performed in order to adjust a structure property of the sensor structure while the second partial structure remains the same.

Abstract: The present invention discloses methods and processes for producing magnetic nanotransistors containing carbon nanotubes. The nanotube is attached to at least one magnetic particle, the nanotube is then placed in between the two fixed magnetic moments, and subjected to an external magnetic field. The current passing through the nanotube can be controlled using the external magnetic field.

Abstract: A MTJ structure is disclosed in which the seed layer is made of a lower Ta layer, a middle Hf layer, and an upper NiFe or NiFeX layer where X is Co, Cr, or Cu. Optionally, Zr, Cr, HfZr, or HfCr may be employed as the middle layer and materials having FCC structures such as CoFe and Cu may be used as the upper layer. As a result, the overlying layers in a TMR sensor will be smoother and less pin dispersion is observed. The Hex/Hc ratio is increased relative to that for a MTJ having a conventional Ta/Ru seed layer configuration. The trilayer seed configuration is especially effective when an IrMn AFM layer is grown thereon and thereby reduces Hin between the overlying pinned layer and free layer. Ni content in the NiFe or NiFeX middle layer is above 30 atomic % and preferably >80 atomic %.

Abstract: A semiconductor pressure sensor includes: a first substrate; a buried insulating film laminated on the first substrate; a second substrate laminated on the buried insulating film; a plurality of electrodes including a lower electrode and at least two upper electrodes, the lower electrode being formed on the second substrate; and a piezoelectric film laminated on the lower electrode and having the upper electrodes formed thereon. In the sensor, there is removed at least a portion of a region of the first substrate corresponding to a region of the second substrate including the piezoelectric film and the electrodes.

Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.

Abstract: A spin memory includes a magneto-resistance element having a first ferromagnetic layer in which a magnetization direction is pinned, a second ferromagnetic layer in which a magnetization direction changes, and a first nonmagnetic layer between the first and second ferromagnetic layers, a lower electrode and an upper electrode extending in a direction between 45 degrees and 90 degrees relative to an axis of hard magnetization of the second ferromagnetic layer, and sandwiching the magneto-resistance element at one end in a longitudinal direction, a switching element connected to another end in a longitudinal direction of the lower electrode, and a bit line connected to another end in a longitudinal direction of the upper electrode, wherein writing is carried out by supplying spin-polarized electrons to the second ferromagnetic layer and applying a magnetic field from the lower electrode and the upper electrode to the second ferromagnetic layer.

Abstract: The description is of a flat substrate with an electrically conductive structure integrated inside the flat substrate or applied to a surface of the flat substrate and/or with a technically improved surface. The invention is characterised in that at least one sensor is integrated inside the flat substrate or applied to a surface of the flat substrate, which generates sensor signals according to deformations occurring inside the flat substrate, at least one actuator is integrated inside the flat substrate or applied to the surface of the flat substrate, which enables the flat substrate to mechanically deform when activated, and a signal unit connected to the at least one sensor and to the at least one actuator is provided, which, on the basis of the sensor signals, generates actuator signals for activating the actuator, so that deformations occurring inside the flat substrate are reduced.

Abstract: A resonator including a substrate, and a resonating unit having an active region that causes resonances and a non-active region that does not cause resonances, and having a first electrode, a piezoelectric film, and a second electrode layered in turn on the substrate. At least one of the first and the second electrodes is formed, so that at least a portion of a non-active region portion thereof has a thickness different from that of an active region portion thereof.

Abstract: A semiconductor memory device comprising: first and second wirings arranged in a matrix; and a memory cell being provided at an intersecting point of the first and second wirings and including a resistance change element and an ion conductor element connected to each other in a cascade arrangement between the first and second wirings.

Abstract: A magnetic switching element includes a ferromagnetic layer which is substantially pinned in magnetization in one direction; and a magnetic semiconductor layer provided within a range where a magnetic field from the ferromagnetic layer reaches, where the magnetic semiconductor layer changes its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto, and a magnetization corresponding to the magnetization of the ferromagnetic layer is induced in the magnetic semiconductor layer by applying a voltage to the magnetic semiconductor layer.

Abstract: In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides.

Abstract: A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.

Abstract: A semiconductor device is provided in which energy band gap can be electrically varied. The device includes nanowires embedded in a material that exhibits a deformation when properly addressed, e.g., a piezoelectric material such as lead zirconate titanate (PZT), aluminum nitride (A1N) or zinc oxide (Zn0). The nanowires can be reversibly strained by applying a local deformation to the piezoelectric material by applying a voltage to the material. The resulting band gap variation can be utilized to tune the color of the light emitted from e.g., a LED or a laser. Further, contact resistance in semiconductor junctions can be controlled, e.g., for use in memories and switches.

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO (001) substrate 11 is prepared. An epitaxial Fe(001) lower electrode (a first electrode) 17 with the thickness of 50 nm is grown on a MgO(001) seed layer 15 at room temperature, followed by annealing under ultrahigh vacuum (2×10?8 Pa) and at 350° C. A MgO(001) barrier layer 21 with the thickness of 2 nm is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) with the thickness of 10 nm is then formed on the MgO(001) barrier layer 21 at room temperature. This is successively followed by the deposition of a Co layer 21 with the thickness of 10 nm on the Fe(001) upper electrode (the second electrode) 23.