Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology.

Abstract: Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.

Abstract: Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.

Abstract: A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.

Abstract: A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.

Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.

Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract: A hybrid transistor device is provided. In one example case, the device includes a substrate, an oxide layer formed on the substrate, and a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap higher than that of silicon. The device includes source-drain/emitter material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain/emitter material contacts the wide-bandgap body material. The device includes a gate material formed over the gate dielectric layer, a base material formed over a portion of the source-drain/emitter material, and a collector material formed over a portion of the base material. The source-drain/emitter material is shared so as to electrically combine a drain of a first transistor type portion of the device and an emitter of a second transistor type portion.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

Abstract: A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential.

Abstract: Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.

Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.

Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current (69) from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current (69) is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.

Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Abstract: A monolithic integrated circuit (IC) chip containing a plurality of transistors, including: a substrate; a first transistor on the substrate; and a second transistor integrally formed on the substrate with the first transistor, the second transistor having a different structure than the first transistor, wherein the first transistor includes a first material system and the second transistor includes a second material system different from the first material system. The monolithic IC chip may further include a third transistor integrally formed on the substrate with the first and second transistors. The first transistor may include gallium nitride (GaN) and the second and third transistors may include silicon carbide (SiC).

Abstract: The invention discloses an ESD protection circuit, comprising a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.

Abstract: A semiconductor element and an operating method thereof are provided. The semiconductor element comprises a first metal oxide semiconductor (MOS) and a second MOS. The second MOS is electrically connected to the first MOS. The second MOS includes a floating bipolar junction transistor (BJT).

Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract: In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transistor region. This makes it possible to maintain the processing accuracy of a MOS transistor while stabilizing the diode current characteristics of the bipolar transistor.

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device includes a substrate having a first region including a first element and a second region including a second element and including a lower substrate and an upper substrate bonded to each other, an epitaxial layer and an insulating layer disposed between the lower substrate and the upper substrate, the epitaxial layer disposed in the first region, and the insulating layer disposed in the second region, a device isolation pattern separating the first element from the second element, and a doped pattern disposed between the upper substrate and the insulating layer and between the upper substrate and the epitaxial layer. The first element is electrically connected to the lower substrate through the doped pattern and the epitaxial layer. The second element is electrically insulated from the lower substrate by the doped pattern and the insulating layer.

Abstract: A semiconductor integrated circuit includes: a first conductive line coupled with a first pad for receiving a first voltage; a second conductive line coupled with a second pad for receiving a second voltage; a third conductive line arranged to be placed in a floating state; a first electrostatic discharge unit coupled between a third pad for inputting/outputting a signal and the third conductive line through a first common conductive line, wherein the first electrostatic discharge unit is configured to provide a bi-directional electrostatic discharge path between the third pad and the third conductive line according to an electrostatic discharge mode; a second electrostatic discharge unit coupled between the first conductive line and the third conductive line through a second common conductive line; and a third electrostatic discharge unit coupled between the second conductive line and the third conductive line through a third common conductive line.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure.

Abstract: The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.

Abstract: A semiconductor device includes a laterally double diffused metal oxide semiconductor (LDMOS) transistor formed on a partial region of a epitaxial layer of a first conductive type, a bipolar transistor formed on another partial region of the epitaxial layer of the first conductive type, and a guard ring formed between the partial region and the another partial region. The guard ring serves to restrain electrons generated by a forward bias operation of the LDMOS transistor from being introduced into the bipolar transistor.

Abstract: An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode.

Abstract: The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.

Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.

Abstract: An epilayer structure includes a field-effect transistor structure and a heterojunction bipolar transistor structure. The heterojunction bipolar transistor structure contains an n-doped subcollector and a collector formed in combination with the field-effect transistor structure, wherein at least a portion of the subcollector or collector contains Sn, Te, or Se. In one embodiment, a base is formed over the collector; and an emitter is formed over the base. The bipolar transistor and the field-effect transistor each independently contain a III-V semiconductor material.

Abstract: The invention is directed to a semiconductor device which is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer is formed being in contact with a bottom portion of a P type base region under an N+ type emitter region. The N type base width control layer shallows a portion of the P type base region under the N+ type emitter region partially. The P type base region is formed by using a process of forming a P type well region, and the N type base width control layer is formed by using a process of forming an N type well region, thereby achieving the process rationalization.

Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: A III-V compound semiconductor structure comprises epitaxial structures that include an integrated pair of different types of active devices. The semiconductor structure includes a semi-insulating substrate of a compound semiconductor III-V material and a first compound semiconductor III-V epitaxial structure disposed on the substrate. A concentration profile of dopant material in the semiconductor structure decreases substantially smoothly across an interface between the substrate and the first epitaxial structure in a direction from the first epitaxial structure toward the substrate, and continues to decrease substantially smoothly from the interface with increasing depth into the substrate despite the presence of silicon or oxygen contaminant at the interface. The interface is substantially free of a second contaminant that was present, during formation of the first epitaxial structure, in a chamber in which the first epitaxial structure was formed.

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion.

Abstract: Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.

Abstract: A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

Abstract: A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.