Abstract: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.

Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.

Abstract: A capacitor assembly (82) is formed on a substrate (20). The capacitor assembly a first conductive plate (38) and a second conductive plate (60) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace (40) is formed over the substrate that is connected to the first conductive plate and extends away from the capacitor assembly. A conductive shield (62) is formed over at least a portion of the conductive trace that is separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.

Abstract: A NOT circuit realized using an atomic switch serving as a two terminal device and including a first electrode made of a compound conductive material having ionic conductivity and electronic conductivity and a second electrode made of a conductive substance. Ag2S, Ag2Se, Cu2S, or Cu2Se is preferably used as the compound conductive material.

Abstract: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained.

Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Abstract: A semiconductor device packaged in three dimensions comprises a first thin film device, a second thin film device, and a third thin film device, each of the first, second, and third thin film devices comprising a first insulating film, a first electrode formed over the first insulating film, a second insulating film formed over the first electrode, first and second thin film transistors formed over the second insulating film, wherein the first thin film transistor is connected to the first electrode through a first contact hole, a third insulating film formed over the first and second thin film transistor, a second electrode formed over the third insulating film, wherein the second electrode is connected to the second thin film transistor through a second contact hole, and a fourth insulating film formed over the third insulating film and the second electrode.

Abstract: An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.

Abstract: Generally provided is a circuit assembly construction for controlling impedance in an electronic package. A large scale, parallel-plate capacitor includes two electrodes separated by a dielectric material. The electrodes serve as reference voltage planes for the electronic package. At least one of the electrodes is patterned such that both electrodes are accessible from a common side of the capacitor. The capacitor is positioned with a first electrode mounted adjacent to an interconnect circuit portion of the electronic package. An electronic device portion of the electronic package is electrically connected, directly or indirectly, to one or more of the electrodes of the capacitor.

Abstract: An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.

Abstract: A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: A lower electrode of a capacitor element and a wiring are formed in a wiring layer that is one layer below an uppermost wiring layer. Subsequently, after the formation of a capacitance insulating film, a TiN film is formed on the entire surface thereof, and then the TiN film is patterned, thereby forming an upper electrode of a capacitor element and a lead wiring for electrically connecting the upper electrode to a wiring of a third wiring layer. Furthermore, in the uppermost layer, a shield is formed covering the upper portion of the capacitor element.

Abstract: As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.

Abstract: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient.