Abstract: An integrated circuit memory device may include a semiconductor substrate and a plurality of word-line layers wherein adjacent word-line layers are separated by respective word-line insulating layers. A plurality of active pillars may extend from a surface of the semiconductor substrate through the plurality of word-line layers and insulating layers. Dielectric information storage layers may be provided between the active pillars and the respective word-line layers. Related methods of operation and fabrication are also discussed.

Abstract: A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.

Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y >x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.

Abstract: A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: A semiconductor device includes a first semiconductor layer, a first interlayer insulation layer, a second semiconductor layer, and a gate pattern. The first interlayer insulation layer covers the first semiconductor layer. The second semiconductor layer is formed on the first interlayer insulation layer and includes source regions, drain regions, and a channel region interposed between the source region and the drain region. The gate pattern includes a gate insulation layer on the channel region of the second semiconductor layer. At least one of the source regions and the drain regions includes an elevated layer having a top surface higher than that of the channel region.

Abstract: A 3D semiconductor device includes a conductive plate defining four sides and four recesses formed in the four sides, respectively. The conductive plate has first and second surfaces opposite to each other. A plurality of conductive leads are located in the recesses, respectively, and the conductive leads have first and second surfaces opposite to each other. A semiconductor die is attached onto the central area of the conductive plate. A plurality of conductive wires electrically connects the semiconductor die to the conductive leads. An encapsulant encloses, as in a capsule, the conductive plate, the conductive leads, the semiconductor die, and the conductive wires in such a manner that the first and second surfaces of the conductive plate and the first and second surfaces of the conductive leads are exposed to the outside.

Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.

Abstract: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission test. If a defective device is detected in this test, a repair device is mounted at a position corresponding to a position of the defective device. At this time, after wiring lines connected to the defective device are cut off, the repair device is electrically connected to portions of the wiring lines, the portions of the wiring lines being located at positions nearer to the drive circuit side than the cut-off positions of the wiring lines.

Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Abstract: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film and an edge portion of the gate electrode is rounded and oxidized.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A method of fabricating an epitaxial compound semiconductor III-V wafer suitable for the subsequent fabrication of at least two different types of integrated active devices (such as an HBT and a FET) on such wafer by providing a substrate; growing a first epitaxial structure on the substrate; and growing a second epitaxial structure on the first epitaxial structure.

Abstract: A semiconductor device includes a first semiconductor pillar, a first gate insulating film, a gate electrode, and a first contact. The first semiconductor pillar extends upwardly from a semiconductor substrate. The first gate insulating film covers side surfaces of the first semiconductor pillar. The gate electrode covers the first gate insulating film. The first gate insulating film insulates the gate electrode from the first semiconductor pillar. The first contact partially overlaps, in plane view, the first semiconductor pillar and the gate electrode. The first contact includes a silicon layer having a top level which is higher than a top level of the gate electrode.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.

Abstract: A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first bit line layer in a first device level. The first bit line layer comprises first bit lines. The first bit line mask is also used to form a second bit line layer in a second device level. The second bit line layer comprises second bit lines. The first bit lines and the second bit lines have different electrical connections to a bit line connection level despite employing the same mask pattern.

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern (1) and insulation (2), and, inside the insulation, a first component (3), the contact terminals (4) of which face towards the conductor pattern (1) and are conductively connected to the conductor pattern (1). The multi-chip package also comprises inside the insulation (2) a second semiconductor chip (13), the contact terminals (14) of which face towards the same conductor pattern (1) and are conductively connected through contact elements (15) to this conductor pattern (1). The semiconductor chips are located in such a way that the first semiconductor chip (3) is located between the second semiconductor chip (13) and the conductor pattern (1).

Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

Abstract: A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer formed on the first conductor layer, a first insulating layer laminated on the first wiring layer, and a second integrated circuit including a plurality of areas formed on a second conductor layer which is laminated on the first insulating layer, and a second wiring layer formed on the second conductor layer. The first integrated circuit and the second integrated circuit are connected electrically by interconnection penetrating in the laminating direction and at least one of bidirectional communication of data, control signal supply, and clock signal supply between the first integrated circuit and the second integrated circuit is carried out through the penetrating interconnection.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.

Abstract: A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM) includes a plurality of memory sets. Within each memory set, a plurality of vertically stacked memory levels are interleaved and all adjacent memory levels share address-selection lines; between adjacent memory sets, memory levels are separated by an inter-level dielectric and do not share any address-selection lines.

Abstract: A semiconductor device packaged in three dimensions comprises a first thin film device, a second thin film device, and a third thin film device, each of the first, second, and third thin film devices comprising a first insulating film, a first electrode formed over the first insulating film, a second insulating film formed over the first electrode, first and second thin film transistors formed over the second insulating film, wherein the first thin film transistor is connected to the first electrode through a first contact hole, a third insulating film formed over the first and second thin film transistor, a second electrode formed over the third insulating film, wherein the second electrode is connected to the second thin film transistor through a second contact hole, and a fourth insulating film formed over the third insulating film and the second electrode.

Abstract: A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug.

Abstract: A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level.

Abstract: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer including a channel region, and a first region and a second region to which an impurity element is introduced to make the first region and the second region a source and a drain, a third region, and a gate electrode provided to partly overlap with the semiconductor layer with a gate insulating film interposed therebetween In the semiconductor layer, the first region is electrically connected to the gate electrode through a first electrode to which an AC signal is input, the second region is electrically connected to a capacitor element through a second electrode, the third region overlaps with the gate electrode and contains an impurity element at lower concentrations than each of the first region and the second region.

Abstract: A multi-domain vertical alignment pixel structure including an active device, a passivation layer, a first pixel electrode, a second pixel electrode, a capacitor-coupling electrode and a semiconductor layer is provided. The active device is disposed on the substrate and has an insulating layer, the passivation layer covers the active device and a part of the insulating layer, the first pixel electrode and second pixel electrode are disposed on the passivation layer and electrically insulated from each other. In addition, the capacitor-coupling electrode is disposed between the second pixel electrode and the substrate. The semiconductor layer is disposed between the insulating layer and the passivation layer, wherein the insulating layer and the passivation layer have a trench and a lateral etched groove located on the sidewall of the trench, and the lateral etched groove exposes the side edge of the semiconductor layer.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

Abstract: A radio frequency arrangement is disclosed, having a first semiconductor body with an integrated circuit formed therein and also with first and second terminal locations. A second semiconductor body with a charge store integrated therein and with a first and second contact locations is arranged with its contact locations mutually facing the terminal locations of the first semiconductor body. The first terminal and the first contact location and also the second terminal and the second contact location are coupled to one another in order thus to form an integrated circuit and also a charge store for supplying the integrated circuit. Realizing the integrated circuit and the charge store separately enables a simple and cost-effective manufacturing procedure for the individual components.

Abstract: Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.

Abstract: Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Abstract: According to the present invention, there is provided a semiconductor device having: first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer; an active region which is formed on the semiconductor substrate so as to be connected to the first and second fins, and supplies a predetermined voltage to the first and second fins; and a gate electrode formed on an insulating film formed on the semiconductor substrate, in a position separated from the active region by a predetermined spacing, so as to cross the first and second fins, wherein in the active region, a predetermined portion between a first portion connected to the first fin and a second portion connected to the second fin is removed.

Abstract: In a semiconductor integrated circuit device, a VDD wiring trace and a GND wiring trace are routed along an N-well and a P-well, respectively, within a substrate. A substrate-bias VDD2 wiring trace is routed in a direction that intersects the VDD wiring trace and GND wiring trace in the same layer thereof and is electrically connected thereto. A P+ diffusion layer is disposed in the N-well in the vicinity of a portion where the wiring directions of the VDD wiring trace and substrate-bias VDD2 wiring trace intersect and is electrically connected to the VDD wiring trace via a contact. An N+ diffusion layer is disposed in the P-well in the vicinity of a portion where the wiring directions of the GND wiring trace and substrate-bias VDD2 wiring trace intersect and is electrically connected to the GND wiring trace via a contact. The P+ diffusion layer is used as a wiring route regarding the VDD wiring trace and the N+ diffusion layer is used as a wiring route regarding the GND wiring trace.

Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.

Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.

Abstract: An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250?, and a ferromagnetic top plate 20a.

Abstract: A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.

Abstract: A fin-type field effect transistor (FINFET) includes a plurality of fins forming drain-source regions and a gate region disposed about the fins. At least a first one of the fins has a first crystal orientation, and at least a second one of the fins has a second crystal orientation that is different from the first crystal orientation. The second crystal orientation is selected to be different from the first crystal orientation to reduce a drive strength quantization error of the transistor. Circuits using such FETS and methods for designing such circuits are also presented.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transparent embossing tool.

Abstract: A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of forming an alignment post on the substrate before the first step, the alignment post being used for positioning the chip connection wiring.