Abstract: In one embodiment, electrostatic discharge (ESD) devices are disclosed.

Abstract: A repairable memory cell in accordance with one or more embodiments of the present disclosure includes a storage element positioned between a first and a second electrode, and a repair element positioned between the storage element and at least one of the first electrode and the second electrode.

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.

Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.

Abstract: A semiconductor device has a trench junction barrier Schottky diode that includes an integrated substrate p-n diode (TJBS-Sub-PN) as a clamping element, the trench junction barrier Schottky diode being suited, e.g., as a Zener diode having a breakdown voltage of approximately 20 V, for use in motor-vehicle generator systems. In this context, the TJBS-Sub-PN is made up of a combination of a Schottky diode, an epitaxial p-n diode and a substrate p-n diode, and the breakdown voltage of the substrate p-n diode (BV_pn) is less than the breakdown voltage of the Schottky diode (BV_schottky) and the breakdown voltage of the epitaxial p-n diode (BV_epi).

Abstract: A non-volatile memory devices includes: a substrate including a circuit device and a metal line electrically connected with the circuit device; a diode connected with the metal line in a vertical direction with respect to a surface of the substrate, and including a metal layer disposed on a lower part of the diode facing the surface of the substrate; and a resistor electrically connected with the diode in series.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.

Abstract: An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric layer. The thin film top plate and bottom plate are composed of thin film resistive layers, such as sichrome, which also are utilized to form back end thin film resistors having various properties. Interconnect conductors of a metallization layer contact the top and bottom plates through corresponding vias.

Abstract: A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer insulation film on the top surface of the insulation film including the first electrode and the side wall; forming a via hole to expose the first electrode by selectively etching the interlayer insulation film such that an edge area at which a side surface and a bottom of the via hole intersect is positioned on a top surface of the side wall; forming a dielectric layer on an inner wall of the via hole; forming a second electrode on the dielectric layer such that the via hole is filled; and forming a metal wire on the second electrode such that the metal wire is electrically connected to the second electrode.