Abstract: An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.

Abstract: Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

Abstract: A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source/drain regions in the active region and second source/drain regions in the passive region, after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.

Abstract: A thin-film resistor and a method for fabricating a thin-film resistor are provided.

Abstract: A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

Abstract: All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n?1, and the third number is 1, the total number of resistors is 2n.

Abstract: Aspects of the present disclosure provide miniaturized isolator modules capable of transferring power and/or data signals across an isolation barrier by way of a transformer while maintaining intrinsic safety (IS) compliance. For example, the isolator modules may provide power from a non-IS side to an IS side of the isolation barrier while protecting the IS side in the event of an overvoltage and/or overcurrent event on the non-IS side. In some aspects, an isolator module includes one or more silicon protection devices, which facilitate the miniaturization of the isolator module while maintaining protection against overvoltage and/or overcurrent events in accordance with IS standards. In some aspects, an isolator module includes a transformer adapted for IS compliance. For example, coils of the transformer may be disposed on opposing sides of an isolation barrier having a thickness of at least 200 microns.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

Abstract: A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.

Abstract: The present disclosure relates to the field of visual images. A stereoscopic display screen includes: an optical component, configured to provide an optical signal of which the light intensity is lower than the light intensity of video information; a transparent display component, configured to display the video information; and a space imaging frame component, configured to form a hollow enclosed cavity which is visible from the front and has a rear end sealed by the transparent display component. A foreground stage imaging area is formed in an internal region of the space imaging frame component, the space imaging frame component forms, at a position opposite the optical component, a virtual space imaging frame component which takes an axial plane of the transparent display component as a mirror symmetrical plane, and a virtual background stage imaging area is formed in the virtual space imaging frame component.

Abstract: A switching device according to an embodiment includes a switching layer disposed between a first electrode and a second electrode. The switching layer contains a material containing a first cation element Z, Te, and N. This material contains at least 5 atomic % or more of each of Z, Te, and N, and when an atomic ratio of Te is X, an atomic ratio of N is Y, an atomic ratio of Z is W, a ratio of Z2Te3 to ZN on a straight line connecting a compound of the first cation element Z with tellurium and nitride of the first cation element Z in a ternary phase diagram of Z, Te, and N is A, and a change in an N content from the Z2Te3—ZN line is B, the material has a composition satisfying X=1.2 (1?A) (0.5+B), Y=A (0.5+B), and W=1?X?Y, where ?0.06?B?0.06 is satisfied when ?>A and ¾<A, and ?0.06?B and Y?0.45 are satisfied when ??A?¾.

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n?1, and the third number is 1, the total number of resistors is 2n.

Abstract: This power supply IC is a semiconductor integrated circuit device serving as a main part for controlling a switching power supply and is formed by integrating a feedback resistor and an output feedback control unit on a single semiconductor substrate, said feedback resistor generating a feedback voltage by dividing the output voltage of the switching power supply (or the induced voltage appearing across an auxiliary winding provided on the primary side of a transformer included in an insulation-type switching power supply), said output feedback control unit performing output feedback control of the switching power supply in accordance with the feedback voltage. The feedback resistor is a polysilicon resistor having a withstand voltage of 100 V or more. A high-voltage region having higher withstand voltage in the substrate thickness direction than the other region is formed in the semiconductor substrate, and the feedback resistor is formed on the high-voltage region.

Abstract: According to an aspect, there is provided a printed circuit board-based resistive device. The resistive device comprises, arranged on a substrate of the printed circuit board of the printed circuit board: a first conductive pad; a second conductive pad; a resistive patch having a first longitudinal end connected to the first conductive pad and a second longitudinal end connected to the second conductive pad, wherein a width of the resistive patch varies along a length of the resistive patch and has a maximum at a point between the first and second longitudinal ends.

Abstract: In an embodiment, an apparatus is disclosed that comprises a plurality of resistors arranged as a reverse bridge and configured to convert an input voltage to a scaled output voltage. The scaled output voltage is scaled to a target format based at least in part on a range of the input voltage and a fixed value of the plurality of resistors. The input voltage is generated based at least in part on at least one signal generated by a sensor based at least in part on a measurement of a property of a measurement target. At least one of the plurality of resistors has a resistance value of R and at least another of the plurality of resistors has a resistance value of R plus or minus ?R.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A multilayer electronic component includes a body including dielectric layers and internal electrodes alternately disposed with the dielectric layers and an external electrode disposed on the body. The external electrode includes an electrode layer connected to the internal electrode, an Sn plating layer disposed on the electrode layer, an Ni plating layer disposed on the Sn plating layer, and a plating layer including Pd disposed on the Ni plating layer.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

Abstract: Particularly, it is an object to provide a circuit substrate that can reduce a field intensity near an electrode having a high potential. A circuit substrate of the present invention includes an insulated substrate, a thin-film resistive element, and electrodes electrically connected to both sides of the thin-film resistive element, the thin-film resistive element and the electrodes being disposed on a surface of the insulated substrate. The circuit substrate is characterized in that the thin-film resistive element has a pattern in which a resistance wire is repeatedly folded back, and a dummy wire for reducing a field intensity is provided on a high-potential electrode side.

Abstract: This power supply IC is a semiconductor integrated circuit device serving as a main part for controlling a switching power supply and is formed by integrating a feedback resistor and an output feedback control unit on a single semiconductor substrate, said feedback resistor generating a feedback voltage by dividing the output voltage of the switching power supply (or the induced voltage appearing across an auxiliary winding provided on the primary side of a transformer included in an insulation-type switching power supply), said output feedback control unit performing output feedback control of the switching power supply in accordance with the feedback voltage. The feedback resistor is a polysilicon resistor having a withstand voltage of 100 V or more. A high-voltage region having higher withstand voltage in the substrate thickness direction than the other region is formed in the semiconductor substrate, and the feedback resistor is formed on the high-voltage region.

Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

Abstract: Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.

Abstract: Provided is a semiconductor device having a resistor including silicide layers and a polysilicon layer with impurities, and the resistor includes a plurality of boundary surfaces between the silicide layers and the polysilicon layer in a longitudinal direction of the resistor, permitting correction with one photomask when a resistance value of a resistor is deviated from a design value while suppressing upsizing of a semiconductor device. Further, provided is a method of manufacturing the semiconductor device, in which the resistance value is adjusted by changing one mask for forming the silicide layers to change the number of boundary surfaces between the silicide layers and the polysilicon layer, and change a length of the polysilicon layer.

Abstract: A method and corresponding system are provided for determining a three-dimensional stress field of an object having a flat surface. At least four flat resistors are placed on the flat surface of the object, with at least one of the resistors having a geometry different from that of the others. A variation of resistance of the resistors is measured. The three-dimensional stress field is determined from a system of equations involving the stress field, values of variations of the measured resistive values and sensitivity parameters of the resistors.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: Disclosed is an optical communication receiver capable of compensating a DC offset while preventing an input load effect. The optical communication receiver includes an optical signal detector; an amplifier inputted with a photocurrent outputted from the optical signal detector; and a DC offset compensation unit provided therein with a third transistor and a fifth transistor which are connected in series to each other to prevent an input load effect, wherein the DC offset compensation unit compensates a DC offset by outputting at least a portion of DC current inputted to the amplifier to ground through the third transistor and the fifth transistor when the photocurrent is an over current more than a predetermined set value.

Abstract: An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.

Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode (301,303) and an alloy electrode (502,602). The device also includes an active region (510,610) sandwiched between the electrode and the alloy electrode. The alloy electrode forms dopants in a sub-region of the active region adjacent to the alloy electrode. The active region can be operated by selectively positioning the dopants within the active region to control the flow of charge carriers between the electrode and the alloy electrode.

Abstract: A resistive memory device includes a stack comprising conductor layers and insulator layers, with the edges of the conductor layers and insulating layers exposed on the sides of the stack. An insulator is disposed on a first side of the stack to cover exposed edges of the conductor layers on the first side of the stack. A memory layer disposed over the stack and insulator, such that the memory layer is in electrical contact with edges of the conductor layers on a second side of the stack but is insulated from edges on the first side of the stack by the insulator. A conductive ribbon is disposed over the memory layer to form programmable memory elements where the conductive ribbon crosses edges of the conductor layers on the second side of the stack.

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

Abstract: An electric resistance element comprising: a base body, which is formed with a semiconductor material; a first contact element, which is electrically conductively connected to the base body; and a second contact element, which is electrically conductively connected to the base body. The base body has a first main surface into which a cutout is introduced. The first contact element is electrically conductively connected to the base body at least in places in the cutout. The base body has a second main surface, which is arranged in a manner lying opposite the first main surface. The second contact element is electrically conductively connected to the base body at least in places at the second main surface.

Abstract: An anneal recipe is provided to tighten the distribution of resistance values in the manufacture of semiconductor integrated circuits. An adjusted amount of dopant is implanted to compensate for a shift in the distribution of resistance values associated with the anneal recipe. The distribution tightening can be effectuated by including an ammonia gas flow in the anneal recipe.

Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

Abstract: A current sense resistor integrated with an integrated circuit die housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive electrode and a second conductive electrode external to the chip-scale semiconductor package where the first conductive electrode and the second conductive electrode are physically separated from each other by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second conductive electrodes. In some embodiments, a semiconductor device including an integrated circuit die housed in a chip-scale semiconductor package includes a current sense resistor formed in a metal layer formed over a passivation layer of the integrated circuit die.

Abstract: Provided is a semiconductor device including a metal dummy pattern and a thin film resistor. In detail, a semiconductor device includes a semiconductor substrate, a thin film resistor, and a metal dummy pattern. The thin film resistor disposed over the semiconductor substrate and extending in a first direction relative to the semiconductor substrate. The metal dummy pattern disposed between the semiconductor substrate and the thin film resistor, the metal dummy pattern including a reflective pattern extending in the first direction semiconductor substrate and spatially corresponding to a periphery of the thin film resistor.

Abstract: Provided are resistance memory devices and methods of forming the same. The resistance memory devices include a first electrode and a second electrode on a substrate, a transition metal oxide layer interposed between the first electrode and the second electrode, an electrolyte layer interposed between the second electrode and the transition metal oxide layer, and conductive bridges having one end that is electrically connected to the second electrode on the electrolyte.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer has an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive trace portion and a second conductive trace portion formed on a printed circuit board where the first conductive trace portion and the second conductive trace portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second metal trace portions, the first and second conductive trace portions forming terminals of the current sense resistor.

Abstract: A resistor array includes a semiconductor substrate, a plurality of isolation regions, a plurality of dummy active regions and a plurality of unit resistors. The plurality of isolation regions are formed in the semiconductor substrate. The plurality of dummy active regions are formed in the semiconductor substrate between the plurality of isolation regions. The plurality of unit resistors are formed on the plurality of dummy active regions.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line.

Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.