Abstract: A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof.

Abstract: A phase change memory device includes a semiconductor substrate active region, a plurality of first conductivity type silicon pillars, and a plurality of second conductivity type silicon patterns. The plurality of first conductivity type silicon pillars is formed on the semiconductor active region such that each first conductivity type silicon pillar is provided for two adjoining cells. The plurality of second conductivity type silicon patterns is formed on the plurality of first conductivity type silicon pillars such that two second conductivity type silicon patterns are formed on opposite sidewalls of each first conductivity type silicon pillars. Two adjoining cells together share only one first conductivity type silicon pillar and each adjoining cell is connected to only one second conductivity type silicon pattern which constitutes a PN diode which serves as a single switching element for each corresponding cell.

Abstract: A method is disclosed for eliminating a mask layer during the manufacture of thin film resistor circuits. The method of the present invention enables the simultaneous etching of both deep vias and shallow vias using one mask layer instead of two mask layers. A high selectivity film layer of silicon nitride is formed on the ends of a thin film resistor layer. The thickness of the silicon nitride causes the etch time for a shallow via to the thin film resistor to be approximately equal to an etch time for a deep via that is etched through dielectric material to an underlying patterned metal layer.

Abstract: A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

Abstract: An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.

Abstract: Storage cells for a semiconductor device can include a first layer of phase change material on a substrate and a second layer of phase change material being in contact with the first layer, the second layer of phase change material having a higher resistance than the first layer.

Abstract: Provided are a phase change material containing carbon (C), a memory device including the phase change material, and a method of operating the memory device. The phase change material contains a main compound and an additive, wherein the main compound is In—Sb—Te and the additive includes carbon (C). A content a of the carbon (C) may be 0.005?a?0.30 atomic (at) %. The additive may further contain nitrogen (N), oxygen (O), boron (B), or a transition metal. The additive may include carbide instead of the carbon (C).

Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Abstract: An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, and groups of resistors made of polycrystalline silicon and disposed on the first insulating film. At least some of the groups of resistors include at least one dummy resistor made of polycrystalline silicon. A second insulating film is disposed on the resistors and on the at least one dummy resistor of the resistor groups. First metal portions are disposed in respective contact holes disposed in the second insulating film for connecting respective portions of the resistors in the respective resistor groups. Second metal portions are disposed on the second insulating film and over the resistors and the at least one dummy resistor in the respective resistor groups.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: A method of processing a nonvolatile memory device includes forming a first electrode, depositing a layer of sol-gel solution on the first electrode, hydrolyzing the layer of sol-gel solution to form a layer of variable electric resistance material, and forming a second electrode on the layer of variable electric resistance material.

Abstract: Electro-thermal trimming of thermally-trimmable resistors is used to trim one or more of the plurality of resistors in or associated with an analog electric circuit. The TCR of each of a subset of a plurality of electro-thermally-trimmable resistors can be trimmed independently from the resistance in order to adjust the output parameter of an analog electric circuit without changing other parameters that would be affected by a change in resistance.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A method for increasing an electrical resistance of a resistor, by nitridizing a fraction of a surface layer of the resistor with nitrogen particles. An embodiment comprises heating the fraction of the surface layer by a beam of radiation or particles, such that the resistor is within a chamber that includes the nitrogen-comprising molecules. An embodiment comprises using an anodization circuit to electrolytically generate nitrogen ions in an electrolytic solution in which the resistor is immersed, wherein the nitrogen particles include the electrolytically-generated nitrogen ions. An embodiment comprises immersing the resistor in a chemical solution which includes the nitrogen particles, wherein the nitrogen particles may include nitrogen-comprising liquid molecules, nitrogen ions, or a nitrogen-comprising gas dissolved in the chemical solution under pressurization.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: An electro-optical device includes: a substrate; a plurality of wiring lines which is formed on the substrate; and an IC which is mounted on the substrate so as to be electrically connected to the plurality of wiring lines. At least a pair of wiring lines among the plurality of wiring lines include a first conductive layer formed on the substrate and a second conductive layer formed on at least the first conductive layer. The first conductive layer and the second conductive layer have different resistance values. The first conductive layer of one of the pair of wiring lines has a plurality of first resistors each extending toward the other wiring line, and the second conductive layer of the other wiring line has a second resistor extending toward the one wiring line. The plurality of first resistors is connected to the second resistor.

Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: In a monolithic electronic component in which a resistive element is incorporated by forming a resistor film on a terminal electrode, a plating film can be formed on the terminal electrode having the resistor film via electroplating in an efficient manner and with a uniform film thickness. In order to form the terminal electrode, the resistor film is disposed directly on the surface of the component body, and a conductive resin film having a relatively low volume resistivity is disposed over the resistor film. The conductive resin film is preferably adapted to have a specific resistance of less than about 1×10?4 ?·m, on which a plating film having a uniform film thickness can be formed efficiently via electroplating.

Abstract: A semiconductor device incorporates a resistor on a structure that uses diffusion layers for sustaining the breakdown voltage thereof to realizes a very resistive element that exhibits a high breakdown voltage and high electrical resistance, includes a spiral very resistive element buried in an interlayer insulator film. A first end of the very resistive element is connected to a drain electrode wiring and the second end of the very resistive element is grounded. An intermediate point of the very resistive element is connected to ae voltage comparator of a control IC. The semiconductor device according to the invention facilitates reducing the components parts costs, assembly costs and size of a switching power supply that includes a very resistive element.

Abstract: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.

Abstract: A semiconductor integrated circuit device having a metal thin-film resistance includes a lower insulation film formed over a semiconductor substrate via another lawyer, a metal interconnection pattern formed on the lower insulation film, an underlying insulation film formed on the lower insulation film and the metal interconnection pattern, and a contact hole formed in said underlying insulation film on the metal interconnection pattern, wherein the metal thin-film resistance is formed so as to extend from a top surface of the underlying insulation film to the contact hole in electrical contact with the metal interconnection pattern in the contact hole, at least a part of constituting elements of the semiconductor integrated circuit other than the metal thin-film resistance is disposed in a region underneath the metal thin-film resistance.

Abstract: A method and structure for increasing an electrical resistance of a resistor that is within a semiconductor structure, by oxidizing or nitridizing a fraction of a surface layer of the resistor with oxygen/nitrogen (i.e., oxygen or nitrogen) particles, respectively. The semiconductor structure may include a semiconductor wafer, a semiconductor chip, and an integrated circuit. The method and structure comprises five embodiments. The first embodiment comprises heating an interior of a heating chamber that includes the oxygen/nitrogen particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen). The second embodiment comprises heating the fraction of the surface layer by a beam of radiation (e.g., laser radiation), or a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen/particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen).

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: A semiconductor device includes a lower electrode including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion, and an insulating layer located over a top edge surface of the sidewall portion of the lower electrode. The insulating layer includes a contact window which partially exposes the top edge surface of the sidewall portion of the lower electrode. The device further includes a heated pattern which contacts the partially exposed top edge surface of the sidewall portion of the lower electrode through the contact window of the insulating layer.

Abstract: Voltage-controlled semiconductor structures, voltage-controlled resistors, and manufacturing processes are provided. The semiconductor structure comprises a substrate, a first doped well, and a second doped well. The substrate is doped with a first type of ions. The first doped well is with a second type of ions and is formed in the substrate. The second doped well is with the second type of ions and is formed in the substrate. The first type of ions and the second type of ions are complementary. A resistor is formed between the first doped well and the second doped well. A resistivity of the resistor is controlled by a differential voltage. A resistivity of the resistor relates to a first depth of the first doped well, a second depth of the second doped well, and a distance between the first doped well and the second doped well. The resistivity of the resistor is higher than that of a well resistor formed in a single doped well with the second type of ions.

Abstract: A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

Abstract: A terminating resistance element of an LSI chip has an N? type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N? type impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the N+ type impurity diffusion layer. The N? type impurity diffusion region has an impurity concentration lower than the impurity concentration of the N+ type impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.

Abstract: A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

Abstract: Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: An electrical resistor structure overlies a substrate and comprises a composite resistor having a first resistor of relatively low resistance and a second resistor of relatively high resistance overlying the first resistor. First and second electrodes make contact with the composite resistor at spaced locations, and a bond pad overlies the second resistor at a position between the electrodes. A metallized fiber is soldered a to a metal bond pad by providing a stacked resistor structure beneath the bond pad, disposing a solder preform over the bond pad, disposing the metallized fiber over the bond pad, and flowing a current through the stacked resistor structure. The stacked resistor structure, when subjected to a current flowing generally along a first axis, is characterized by a temperature profile that has first and second peaks on either side of the bond pad.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Abstract: A semiconductor component having a tuned variable resistance resistor and a method for manufacturing the tuned variable resistance resistor. A semiconductor process for manufacturing a semiconductor component is selected. For the selected process, the tuned variable resistance resistor is characterized to determine the maximum stress current as a function of the width of the tuned variable resistance resistor. Then, for a given width and maximum stress current, the voltages across the resistors are characterized as a function of length. A tuned variable resistance resistor having a length and width capable of sustaining a predetermined maximum stress current is integrated into a semiconductor component. The semiconductor component may include protection circuitry designed in accordance with the Human Body Model, the Charge Device Model, or both.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: An integrated circuit has a circuit component and a heating component thermally coupled together in a region thermally isolated from other parts of the integrated circuit. The thermal isolation can be provided by a bridge over a cavity in the substrate or caps over a thin substrate. A control circuit, which may be responsive to a sensing component thermally coupled to the heating component, controls the heating component to heat the circuit component to a temperature greater than that of the other parts of the integrated circuit, to control a temperature-dependent characteristic of the circuit component. The circuit component can for example be a resistor whose resistance is precisely determined and/or adjusted via the control circuit.

Abstract: The accuracy of the width measurement of a semiconductor resistor is improved by modifying the gate mask of a standard MOS transistor fabrication process to form an opening between regions of polysilicon that are used as a mask when the substrate or well material is implanted to form the resistor.

Abstract: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient.

Abstract: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.

Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited A and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.

Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.