Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

Abstract: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

Abstract: A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

Abstract: A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer, and a sidewall spacer is formed at sidewalls of the gate stack. The device further includes a common source line that electrically interconnects a plurality of sources of a plurality of the flash memory cells, and is formed in the isolation layer by removing an insulating material in the isolation layer and is formed in parallel to a word line formed over the gate stack. A silicide layer is formed in the common source line.

Abstract: In a capacitor-containing semiconductor integrated circuit, a portion in which a plurality of capacitors are serially connected together is arranged so that at least part of the capacitors is formed as a well capacitor.

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric (1510) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (160).

Abstract: A split-gate flash memory device has a floating gate with a lateral recess at its bottom sidewall by adding an undercutting step. The split-gate flash memory device has a floating gate with a lateral recess on a substrate, an integrated dielectric layer lining the substrate, the sidewall and the lateral recess of the floating gate; a control gate on the integrated dielectric layer and covering at least part of the floating gate; and a dielectric spacer in the lateral recess between the integrated dielectric layer and the control gate.

Abstract: Systems and methodologies are provided for simplifying a polymer memory cell's operation by employing a post polymer growth treatment to form ionic or super ionic metal compounds therein. Such post polymer growth treatment facilitates distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell, and mitigates (or eliminates) a need for initialization procedures. Moreover, the post treatment of the present invention can also facilitate controlling a distribution of various thresholds (e.g., write and erase threshold), and set them to predetermined values Accordingly, variability in threshold values of polymer memory cells that can result from initialization processes can be mitigated (or eliminated), and thicker polymer layers can be employed without an initialization penalty.

Abstract: Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A multi bits flash memory device and a method of operating the same are disclosed.

Abstract: In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.