Area Ccd Imager (epo) Patents (Class 257/E27.154)
  • Patent number: 10573402
    Abstract: A semiconductor apparatus includes a nonvolatile memory therein and an input terminal configured to receive a test control signal and an input signal of a writing/erasing voltage from an external device. The semiconductor apparatus includes: an output terminal; a positive pulse detection circuit configured to detect a positive test control signal, and output the positive test control signal to the output terminal; and a negative pulse detection circuit configured to detect a negative test control signal, and output the negative test control signal to the output terminal after inverting.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 25, 2020
    Assignee: DENSO CORPORATION
    Inventor: Mutsuya Motojima
  • Patent number: 10547803
    Abstract: An imaging arrangement comprising: a plurality of pixels arranged in a matrix; and a signal processing arrangement. A first and a second line of the matrix each comprise a light-receiving pixel and a reference pixel, the light-receiving pixels each receive incident light and output a light signal based on the incident light, and each reference pixel outputs a pixel signal for forming an address signal. The processing arrangement provides a first address signal and a second address signal, wherein: the first address signal indicates the position of the first line and comprises a signal value based on the pixel signal from the first line; and the second address signal indicates the position of the second line and comprises a signal value based on the pixel signal from the second line; and the signal value of the first address signal is different to the signal value of the second address signal.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: January 28, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Shikina, Kentaro Tsukida, Yasushi Iwakura, Yoichi Wada
  • Patent number: 10389943
    Abstract: An actuator for moving a platform having electrical connections is provided. The actuator includes an outer frame connected to an inner frame by one or more spring elements that are electrically conductive. The actuator further includes one or more comb drive actuators that apply a controlled force between the outer frame and the inner frame. Each of the comb drive actuators includes one or more comb drives. Moreover, a method for moving a platform having electrical connections is also provided. The method includes connecting an outer frame to an inner frame using one or more spring elements that are electrically conductive. The method further includes generating a controlled force using one or more comb drive actuators. Each of the comb drive actuators includes one or more comb drives. In addition, the method includes applying the controlled force between the outer frame and the inner frame.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 20, 2019
    Assignee: MEMS Start, LLC
    Inventor: Roman C. Gutierrez
  • Patent number: 10199427
    Abstract: A solid-state imaging device includes: plural photodiodes formed in different depths in a unit pixel area of a substrate; and plural vertical transistors formed in the depth direction from one face side of the substrate so that gate portions for reading signal charges obtained by photoelectric conversion in the plural photodiodes are formed in depths corresponding to the respective photodiodes.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 5, 2019
    Assignee: Sony Corporation
    Inventors: Taiichiro Watanabe, Akihiro Yamada, Hideo Kido, Hiromasa Saito, Keiji Mabuchi, Yuko Ohgishi
  • Patent number: 10180504
    Abstract: Some embodiments include a system having a detection sensor array, which includes multiple detection sensors with each detection sensor having an enabled state and a disabled state, and having a control module configured to operate the detection sensor array. Under the enabled state, each detection sensor is configured to detect and identify electromagnetic radiation, and under the disabled state, each detection sensor is configured not to detect and identify electromagnetic radiation. Further, the detection sensor array comprises a test state and an operational state. Other embodiments of related systems and methods are also disclosed.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 15, 2019
    Assignees: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY, THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMY
    Inventors: Joseph Smith, Eric Forsythe, David Allee
  • Patent number: 9903959
    Abstract: Some embodiments include a method of operating a detection sensor array. The detection sensor array has multiple detection sensors. Each detection sensor of the multiple detection sensors has an enabled state and a disabled state, and each detection sensor of the multiple detection sensors is configured to detect and identify electromagnetic radiation when in the enabled state and not to detect and identify electromagnetic radiation when in the disabled state. The detection sensor array also has a test state in which all of the multiple detection sensors operate in the enabled state when the detection sensor array is in the test state. Other embodiments of related systems and methods are also disclosed.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 27, 2018
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Joseph Smith, Eric Forsythe, David Allee
  • Patent number: 9832403
    Abstract: A solid-state imaging device includes a first pixel and a second pixel. The first pixel includes a light-shielding part having an opening of a predetermined size. The second pixel includes a light-shielding part having an opening of the predetermined size at a position different from a position of the opening of the first pixel.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 28, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Ryuhei Morita
  • Patent number: 9661243
    Abstract: An imaging device and method for operating the imaging device. Some embodiments comprise a pixel array configured as rows and columns of binning pixel units, each binning pixel unit including a plurality of photosensors that generate respective charge signals in response to incident light. Each binning pixel unit is configured to selectively bin the charge from at least two of the photosensors. The pixel array may be readout in a binning-pixel-unit row by binning-pixel-unit row basis. During readout of each binning pixel unit row, each binning pixel unit in the row is operable to selectively bin at least two of the charge signals therein based on a respective one of control signals provided to each of the binning pixel units in the row. In reading out a binning pixel unit row for a given image frame, a first binning pixel unit may perform in-pixel charge domain binning while a second binning pixel unit in the row may not bin the charge from the different photosensors therein.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: May 23, 2017
    Assignee: FORZA SILICON CORPORATION
    Inventors: Guang Yang, Ramy Tantawy
  • Patent number: 9635351
    Abstract: Representative implementations of devices and techniques provide dynamic calibration for imaging devices and systems. A reference pixel is arranged to receive an electrical reference signal and to output a calibration signal. The reference signal may be based on imaging illumination.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies AG
    Inventors: Markus Dielacher, Martin Flatscher, Michael Mark, Josef Prainsack
  • Patent number: 9420261
    Abstract: Left- and right-eye captured images are output upon reception of light beams having passed through one imaging optical system, and the difference, between the left- and right-eye captured images, of each of subjects included in the left- and right-eye captured images is detected. An extraction image extracted from a region which includes a main subject and has a predetermined size is output for each of the left- and right-eye captured images. At this time, the region is set so that the difference, between the left- and right-eye captured images, of a subject which is different from the main subject and included in both the extraction images has a predetermined value.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 16, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiharu Ueda, Takafumi Kishi
  • Patent number: 9232159
    Abstract: An image sensor may include crosstalk calibration pixels. Crosstalk calibration pixels may include exposed pixels and shielded pixels. Exposed pixels may be partially or completely surrounded by shielded pixels. Calibration pixels may be formed in a checkerboard pattern of alternating shielded and exposed pixels or a double checkerboard pattern of alternating pairs of shielded and exposed pixels. Exposed pixels may have apertures of various size in a shielding layer that shields the shielded pixels from light. Signals generated by exposed and shielded pixels may be used in assessing pixel optical and electrical crosstalk and indirectly deducing the spectral composition of incoming light for particular locations in a pixel array. Information about local crosstalk across the array may be used in coordinate dependent color correction matrices, white balance algorithms, luminance and chroma noise cancellation, edge sharpening, assessment of pixel implantation depth, and measuring a modulation transfer function.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Sergey Velichko, Gennadiy Agranov
  • Patent number: 8878264
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Sergey Velichko, Jingyi Bai
  • Patent number: 8841714
    Abstract: A solid state imaging device 1 is provided with a photoelectric conversion portion 2 having a plurality of photosensitive regions 7, and a potential gradient forming portion 3 having an electroconductive member 8 arranged opposite to the photosensitive regions 7. A planar shape of each photosensitive region 7 is a substantially rectangular shape. The photosensitive regions 7 are juxtaposed in a first direction intersecting with the long sides. The potential gradient forming portion 3 forms a potential gradient becoming higher along a second direction from one of the short sides to the other of the short sides of the photosensitive regions 7. The electroconductive member 8 includes a first region 8a extending in the second direction and having a first electric resistivity, and a second region 8b extending in the second direction and having a second electric resistivity smaller than the first electric resistivity.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 23, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tomohiro Ikeya, Yasuhito Yoneta, Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 8710420
    Abstract: Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Aptina Imaging Corporation
    Inventor: Jaroslav Hynecek
  • Patent number: 8574941
    Abstract: A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator. The method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Tomoyuki Hirano
  • Patent number: 8569805
    Abstract: A floating diffusion (331) is created substantially at center of the light-receiving surface of an embedded photodiode (31), with a gate electrode of a transfer transistor (32) surrounding the floating diffusion. The concentration (or depth) of impurities in a p+-type semiconductor region, n-type semiconductor region or p-well region is changed in an inclined form so that a potential gradient being inclined downwards from the circumference to the center is created when an appropriate bias voltage is applied to the pn junction. The photocharges produced by incident light are rapidly moved along the potential gradient toward the center. Even in the case where the photocharge storage time is short, the photocharges can be efficiently collected since the maximum moving distance from the circumference of the photodiode (31) to the floating diffusion (331). Thus, the photocharges produced by the photodiode (31) are efficiently utilized, whereby the detection sensitivity is improved.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: October 29, 2013
    Assignees: Tohoku University, Shimadu Corporation
    Inventors: Shigetoshi Sugawa, Yasushi Kondo, Hideki Tominaga
  • Patent number: 8481358
    Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: July 9, 2013
    Assignee: Truesense Imaging, Inc.
    Inventor: Shen Wang
  • Patent number: 8247847
    Abstract: A solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area ratio higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of metal material. The second transfer electrode portion includes a plurality of second transfer electrodes having a single-layer structure of polycrystalline silicon or amorphous silicon.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: August 21, 2012
    Assignee: Sony Corporation
    Inventors: Kaori Takimoto, Masayuki Okada, Takeshi Takeda
  • Patent number: 8129760
    Abstract: A structure which meets a high-quality reading requirement and realizes high-speed color reading when the reading section of a color image forming apparatus adopts a color contact image sensor using CCDs as reading element arrays is disclosed. The image sensor of a color image reading section uses a color contact image sensor in which a plurality of CCDs are aligned as reading element arrays in the main scanning direction. In this case, each CCD has one analog shift register for RGB time-division reading, and three R, G, and B reading apertures arranged parallel to each other at a pitch corresponding to the reading resolution. The pixel pitch in the main scanning direction is constant.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 6, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Hiromatsu
  • Publication number: 20120038904
    Abstract: A unit pixel included in a photo-detection device, the unit pixel including a floating diffusion region in a semiconductor substrate, a ring-shaped collection gate over the semiconductor substrate, a ring-shaped drain gate over the semiconductor substrate, and a drain region in the semiconductor substrate, wherein the collection gate and the drain gate are respectively arranged between the floating diffusion region and the drain region.
    Type: Application
    Filed: July 21, 2011
    Publication date: February 16, 2012
    Inventors: Eric R. FOSSUM, Yoon-Dong Park
  • Patent number: 7964451
    Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Patent number: 7902574
    Abstract: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (?T), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (?S), and a reset transistor. During the accumulating period of photoelectric charge, voltage (?) over that applied on the semiconductor substrate, or ?0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Satoru Adachi
  • Patent number: 7863076
    Abstract: Disclosed herein is a solid-state image pickup device which includes: a light-receiving unit for photoelectric conversion of incident light; and a charge transfer unit of an n-channel insulating gate type configured to transfer a signal charge photoelectrically converted in the light-receiving unit; wherein the charge transfer unit has an insulating film formed on a transfer electrode and having a negative fixed charge.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Sony Corporation
    Inventor: Susumu Hiyama
  • Patent number: 7846760
    Abstract: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: December 7, 2010
    Assignee: Kenet, Inc.
    Inventors: William D. Washkurak, Michael P. Anthony, Gerhard Sollner
  • Patent number: 7759157
    Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: July 20, 2010
    Assignee: FujiFilm Corporation
    Inventors: Eiichi Okamoto, Shunsuke Tanaka, Shinji Uya
  • Publication number: 20100141631
    Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Inventor: Jeffrey A. McKee
  • Publication number: 20100053405
    Abstract: A demodulation pixel architecture allows for demodulating an incoming modulated electromagnetic wave, normally visible or infrared light. It is based on a charge coupled device (CCD) line connected to a drift field structure. The drift field is exposed to the incoming light. It collects the generated charge and forces it to move to the pick-up point. At this pick-up point, the CCD element samples the charge for a given time and then shifts the charge packets further on in the daisy chain. After a certain amount of shifts, the multiple charge packets are stored in so-called integration gates, in a preferred embodiment. The number of integration gates gives the number of simultaneously available taps. When the cycle is repeated several times, the charge is accumulated in the integration gates and thus the signal-to-noise ratio increases. The architecture is flexible in the number of taps. A dump node can be attached to the CCD line for dumping charge with the same speed as the samples are taken.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 4, 2010
    Applicant: MESA IMAGING AG
    Inventors: Michael Lehmann, Bernhard Buettgen
  • Patent number: 7605411
    Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 20, 2009
    Assignee: Fujifilm Corporation
    Inventors: Hirokazu Shiraki, Makoto Kobayashi, Katsumi Ikeda
  • Publication number: 20090020789
    Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21<channel 22<channel 23, 25 A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 22, 2009
    Applicant: FUJIFILM Corporation
    Inventors: Hirokazu SHIRAKI, Makoto Kobayashi, Katsumi Ikeda
  • Patent number: 7291861
    Abstract: A solid-state imaging device includes a two-dimensional array of photosensor sections on a semiconductor substrate, and a vertical transfer section including two-layer vertical transfer electrodes. The photosensor sections store signal charges generated by photoelectric conversion. The vertical transfer section reads signal charges from the photosensor sections and vertically transfers the read signal charges. The two-layer vertical transfer electrodes have first transfer electrode layers and second transfer electrode layers, and the first transfer electrode layers serve as read electrodes for reading the signal charges from the photosensor sections. The first transfer electrode layers have a larger electrode width with respect to the photosensor sections than the second transfer electrode layers.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: November 6, 2007
    Assignee: Sony Corporation
    Inventor: Junichi Furukawa