Abstract: To manufacture a micro structure and an electric circuit included in a micro electro mechanical device over the same insulating surface in the same step. In the micro electro mechanical device, an electric circuit including a transistor and a micro structure are integrated over a substrate having an insulating surface. The micro structure includes a structural layer having the same stacked-layer structure as a layered product of a gate insulating layer of the transistor and a semiconductor layer provided over the gate insulating layer. That is, the structural layer includes a layer formed of the same insulating film as the gate insulating layer and a layer formed of the same semiconductor film as the semiconductor layer of the transistor. Further, the micro structure is manufactured by using each of conductive layers used for a gate electrode, a source electrode, and a drain electrode of the transistor as a sacrificial layer.

Abstract: An organic electroluminescent display device includes: first and second substrates facing and spaced apart from each other, the first and second substrates including at least one pixel region having first, second and third sub-pixel region; a gate line and a data line on the first substrate, the gate line and the data line crossing each other to define the at least one pixel region; a first electrode on the first substrate in each of the first, second and third sub-pixel regions; first, second and third organic patterns on the first electrode in the first, second and third sub-pixel regions, respectively, the first, second and third organic patterns having a zigzag shape along a first direction parallel to the gate line with respect to a virtual line passing through a central portion of each of the first, second and third sub-pixel regions; and a second electrode on the first, second and third organic patterns

Abstract: A thin film transistor including: an active layer formed on a substrate; a gate insulating layer pattern formed on a predetermined region of the active layer; a gate electrode formed on a predetermined region of the gate insulating layer pattern; an etching preventing layer pattern covering the gate insulating layer pattern and the gate electrode; and a source member and a drain member formed on the active layer and the etching preventing layer pattern.

Abstract: This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: An organic light emitting diode (OLED) display that includes a substrate, a thin film transistor, and a pixel electrode. The thin film transistor is formed on the substrate and includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The pixel electrode is electrically connected to the thin film transistor and is formed on the same layer as the source electrode and the drain electrode. The source electrode and the drain electrode include a first conductive layer, and the pixel electrode includes a first conductive layer and a second conductive layer stacked thereon.

Abstract: A thin film transistor, a manufacturing method thereof, and a display device having the same are disclosed. The thin film transistor includes a semiconductor layer formed on a substrate, a gate insulating layer formed on the substrate including the semiconductor layer, a gate electrode formed on the gate insulating above the semiconductor layer, source and drain electrodes connected to the semiconductor layer, and 3.5 to 4.5 protrusions formed on the semiconductor layer overlapped with the gate electrode. Malfunction of the thin film transistor and inferior image quality of the display device can be prevented by adjusting the number of protrusions to minimize leakage current and defects.

Abstract: Disclosed here in is a flash memory device and a method of fabricating the same. In accordance with one aspect of the invention, a flash memory device includes first contact plugs formed over a semiconductor substrate between gate patterns. Second contact plugs are formed over the semiconductor substrate between gate patterns and disposed alternately with the first contact plugs. The second contact plugs having a height greater than the first contact plugs. First and second conductive pads are connected to the first contact plugs. First and second pad contact plugs are formed on extended edge portions of the first and second conductive pads. First bit lines are connected to the first and second pad contact plugs, and second bit lines are connected to the second contact plugs.

Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.

Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.

Abstract: An electric optical device includes a transistor that includes a semiconductor layer having a source region connected to a data line, a drain region connected to a pixel electrode, and a channel region, and a gate electrode, a first light blocking film that is formed to be wider than the gate electrode and that is connected to the gate electrode via a first contact hole which is opened in a first insulating film disposed on the gate electrode, and a second light blocking film that is provided between the semiconductor layer and a substrate and is connected to the first light blocking film via a second contact hole which is opened to penetrate the first insulating film, a gate insulating film, and a second insulating film.

Abstract: A display substrate includes a gate line, a gate insulating layer, a data line, a thin-film transistor (TFT), a storage line, a passivation layer, a color filter layer, a pixel electrode, a first light-blocking layer and a second light-blocking layer. The storage line includes the same material as the gate line. The passivation layer covers the data line. The color filter layer is formed on the passivation layer. The pixel electrode is formed on the color filter layer in each pixel. The first light-blocking layer is formed between adjacent pixel electrodes, and includes the same material as the gate line. The second light-blocking layer is formed between the first light-blocking layer, and includes the same material as the data line. Therefore, an aperture ratio may be increased.

Abstract: A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion.

Abstract: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto.

Abstract: A radiation image pickup apparatus allowed to restore a change in characteristics in a pixel transistors caused by radiation, and a method of driving the same are provided. The radiation image pickup apparatus includes: a pixel section including a plurality of unit pixels and generating an electrical signal based on incident radiation, each of the unit pixels including one or more pixel transistors and a photoelectric conversion element; a drive section for selectively driving the unit pixels of the pixel section; and a characteristic restoring section including a first constant current source for annealing and a selector switch for changing a current path from the unit pixels to the first constant current source at the time of non-measurement of the radiation, and allowing an annealing current to flow through the pixel transistor, thereby restoring characteristics of the pixel transistor.

Abstract: A high-performance thin film transistor structure which is easily manufactured is provided. The thin film transistor structure includes: a first electrode; second and third electrodes apart from each other in a hierarchical level different from that of the first electrode; first, second, and third wirings connected to the first, second, and third electrodes, respectively; a main stack body disposed so as to be opposed to the first electrode with an interlayer insulating layer in between, between the first electrode, and the second and third electrodes; and a sub stack body including an insulating layer and a semiconductor layer, disposed so as to be opposed to the first wiring with the interlayer insulating layer in between, between the first and second wirings in a position where the first and second wirings overlap and/or between the first and third wirings in a position where the first and third wirings overlap.

Abstract: A method for manufacturing a display device includes; a step of preparing a flexible substrate including a delamination layer on its back surface, a step of bonding a support substrate to the delamination layer of the flexible substrate via an adhesive layer, a step of forming predetermined devices on a front surface of the flexible substrate having the support substrate bonded thereto, and a step of removing the support substrate by delaminating the delamination layer from the flexible substrate having the devices formed thereon.

Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remo

Abstract: A semiconductor device includes a thin film transistor and a thin film diode on a same substrate. A semiconductor layer (109) of the thin film transistor and a semiconductor layer (110) of the thin film diode are crystalline semiconductor layers formed by crystallizing the same non-crystalline semiconductor film. The thickness of the semiconductor layer (110) of the thin film diode is greater than the thickness of the semiconductor layer (109) of the thin film transistor, and the surface of the semiconductor layer (110) of the thin film diode is rougher than the surface of the semiconductor layer (109) of the thin film transistor.

Abstract: A circuit structure includes a substrate; a first amorphous silicon layer over the substrate; a first glue layer over and adjoining the first amorphous silicon layer; and a second amorphous silicon layer over and adjoining the first glue layer.

Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.

Abstract: A photodiode (10) of the present invention has a p-type semiconductor region (11), an i-type semiconductor region (12), and an n-type semiconductor region (13). The channel length “L” of the photodiode (10) is determined by the source wiring films (8) formed by etching. This configuration provides a display device equipped with the plurality of photodiodes (10) having consistent properties.

Abstract: Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.

Abstract: A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.

Abstract: Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.

Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: Disclosed is a TFT substrate for a display apparatus comprising a gate wiring including a gate electrode, a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area overlapping the gate electrode and the semiconductor layer under the source electrode extends outward to an area not overlapping the gate electrode. Advantageously, the present disclosure provides a TFT substrate for a display apparatus having a high aperture ratio and causing less afterimaging, and a manufacturing method of the same.

Abstract: Provided are a thin film transistor that is capable of suppressing desorption of oxygen and others from an oxide semiconductor layer, and reducing the time to be taken for film formation, and a display device provided therewith. A gate insulation film 22, a channel protection layer 24, and a passivation film 26 are each in the laminate configuration including a first layer 31 made of aluminum oxide, and a second layer 32 made of an insulation material including silicon (Si). The first and second layers 31 and 32 are disposed one on the other so that the first layer 31 comes on the side of an oxide semiconductor layer 23. The oxide semiconductor layer 23 is sandwiched on both sides by the first layers 31 made of aluminum oxide, thereby suppressing desorption of oxygen and others, and stabilizing the electrical characteristics of a TFT 20.

Abstract: An electro-optic device is disclosed. The electro-optic device includes an insulating layer, a first semiconducting region disposed above the insulating layer and being doped with doping atoms of a first conductivity type, a second semiconducting region disposed above the insulating layer and being doped with doping atoms of a second conductivity type and an electro-optic active region disposed above the insulating layer and between the first semiconducting region and the second semiconducting region.

Abstract: Thin-film transistors are made using an organosilicate glass (OSG) as an insulator material. The organosilicate glasses may be SiO2-silicone hybrid materials deposited by plasma-enhanced chemical vapor deposition from siloxanes and oxygen. These hybrid materials may be employed as the gate dielectric, as a subbing layer, and/or as a back channel passivating layer. The transistors may be made in any conventional TFT geometry.

Abstract: A liquid crystal display panel includes: a thin film transistor array substrate having a gate line and a data line provided on the substrate; a gate insulating film between the gate line and the data line; a thin film transistor having a source electrode, a drain electrode and a gate electrode; a pixel electrode; a protective film for protecting the thin film transistor; a plurality of pads; a transparent electrode pattern formed on the data line, source electrode and drain electrode; and a color filter array substrate joined to the thin film transistor array substrate so that the color filter substrate does not overlap the pad area of the thin film transistor array substrate, wherein at least one of the gate insulating film and protective film in the pad area is etched using the color filter array substrate as a mask to expose at least one of the plurality of pads.

Abstract: Disclosed herein is a display device including: a support substrate; a drive circuit provided on the support substrate; an interlayer insulating film which covers the drive circuit; organic field light-emitting elements arranged in a display region on the interlayer insulating film; and a lead-out wiring extended from the organic field light-emitting elements to a peripheral region around the display region, wherein the interlayer insulating film includes a laminated film made up of an inorganic insulating film and organic insulating film stacked in this order, the organic insulating film has an isolation trench which surrounds the display region, the isolation trench being devoid of the organic insulating film and having the inorganic insulating film at its bottom, and the drive circuit and lead-out wiring are insulated from each other by the inorganic insulating film where the lead-out wiring crosses the isolation trench.

Abstract: The present invention provides an organic semiconductor element which has a low hygroscopic property and whose property is hardly deteriorated with time and an electronic device and electronic equipment each provided with such an organic semiconductor element and having high reliability. The organic semiconductor element of the present invention includes: a source electrode 20a; a drain electrode 20b; a gate electrode 50; a gate insulating layer 40; an organic semiconductor layer 30; and a buffer layer (another insulating layer) 60, wherein at least one of the gate insulating layer 40 and the buffer layer 60 contains an insulating polymer with a main chain having both end portions and including repeating units represented by the following general formula (1) or (2): where R1 and R2 are the same or different and each of R1 and R2 is a divalent linkage group, and Y is an oxygen atom or a sulfur atom.

Abstract: A semiconductor device 100 includes a thin-film transistor, which is supported by a substrate 101 and which includes a crystalline semiconductor layer 107 with a channel region 115 and source and drain regions 113, a gate insulating film 108 that is arranged to cover the crystalline semiconductor layer 107, and a gate electrode 109 that is arranged on the gate insulating film 108 to control the conductivity of the channel region; and a thin-film diode, which is also supported by the substrate 101 and which includes an amorphous semiconductor layer 110 that has at least an n-type region 114 and a p-type region 118. The amorphous semiconductor layer 110 has been deposited on the gate insulating film 108 in contact with the surface of the gate insulating film 108. The n-type or p-type region 114 or 118 and the source and drain regions 113 have the same dopant element.

Abstract: A pixel structure includes a substrate, a gate and a pixel electrode that are disposed on the substrate, a patterned dielectric layer and a patterned semiconductor layer disposed on the gate, a source and a drain disposed on two sides of the patterned semiconductor layer respectively, and a passivation layer disposed on the source, the drain and the semiconductor layer. The sidewall surfaces of the source and the drain are completely covered with the passivation layer, but a part of the pixel electrode is exposed by the passivation layer.

Abstract: A this film transistor is provided. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a channel region, wherein the channel region is provided between the source region and the drain region; and a gate electrode overlapping with the channel region, wherein the channel region includes at least a portion of a channel width that is configured to at least one of continuously decrease and continuously increase in a lengthwise direction.

Abstract: Example embodiments are directed to oxide thin film transistors and methods of manufacturing the oxide thin film transistors. The oxide thin film transistor includes an active region in a gate insulation layer and under a source and a drain in a bottom gate structure, thus improving electrical characteristics of the oxide thin film transistor.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: An array substrate for a liquid crystal display device includes a gate line and a data line crossing each other on a substrate to define a pixel region, an insulating layer between the gate line and the data line, a gate electrode extending from the gate line, and a transistor in the pixel region having an active layer on the insulating layer, ohmic contact layers of a first material that are adjacent to ends of the active layer, buffer layers of a second material, which is different from the first material, on the ohmic contact layers, a source electrode contacting one of the buffer layers and a drain electrode contacting another one of the buffer layers, wherein the active layer is in an island shape over the gate electrode and within a boundary defined by a perimeter of the gate electrode.

Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material including a first portion contacting the first electrode, a second portion contacting the second electrode, and a third portion between the first portion and the second portion. A width of the third portion is less than a width of the first portion and a width of the second portion.

Abstract: A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.

Abstract: A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.

Abstract: Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Abstract: Each pixel region includes first and second pixel electrodes (17a, 17b) and first-third capacitor electrodes (67x-67z) each positioned on a layer where a data signal line (15) is positioned. One conductive electrode (9) of a transistor, the first pixel electrode (17a), and the second capacitor electrode (67y) are electrically connected with one another. Each of the first and third capacitor electrodes (67x, 67z) is electrically connected with the second pixel electrode (17y). The first-third capacitor electrodes are aligned in this order in a row direction in such a manner as to overlap a retention capacitor line (18) via a first insulating film, and the second capacitor electrode (67y) overlaps the second pixel electrode (17b) via a second insulating film. This allows increasing production yields of an active matrix substrate based on a capacitive coupling pixel division system and a liquid crystal panel including the active matrix substrate.