Abstract: Disclosed is a Cu alloy film for a display device that has high adhesion to a glass substrate while maintaining a low electric resistance characteristic of Cu-based materials. The Cu alloy film is wiring in direct contact with a glass substrate on a board and contains 0.1 to 10.0 atomic % in total of one or more elements selected from the group consisting of Ti, Al, and Mg. Also disclosed is a display device comprising a thin-film transistor that comprises the Cu alloy film. In a preferred embodiment of the display device, the thin-film transistor has a bottom gate-type structure, and a gate electrode and scanning lines in the thin-film transistor comprise the Cu alloy film and are in direct contact with the glass substrate.

Abstract: An array substrate of a display device, the array substrate: a substrate having a first region and a second region spaced apart from the first region; a blocking layer located on the substrate; a first electrode located on the blocking layer in the second region; an insulating film located on the blocking layer to cover the first electrode; a second electrode located on the insulating film to overlap the first electrode; and a third electrode overlapping the first electrode between the substrate and the blocking layer. Accordingly, it is possible to reduce an area that is occupied by a storage capacitor in a pixel region and to achieve high luminance by increasing the aperture ratio, by providing a structure and method of increasing a storage capacitance of the same area.

Abstract: A semiconductor device has a semiconductor layer, a plurality of charge-accumulating layers formed at a predetermined interval from each other on said semiconductor layer through a first insulating film, a second insulating film formed on said charge-accumulating layer, a control gate including a silicide film formed on said second insulating film, a third insulating film formed between said control gates so that the top surface of said third insulating film is lower than the top surface of said control gate but is higher than the top surface of said second insulating film, a fourth insulating film formed into a concave shape so as to cover the top surface of said third insulating film and the side surfaces of said control gate positioned higher than the top surface of said third insulating film, and a fifth insulating film formed on said control gate and said fourth insulating film.

Abstract: A bottom gate-type thin film transistor includes a gate insulating film, an interlayer insulating film formed on the gate insulating film, having an opening which is formed in a formation region of a gate electrode, and a semiconductor film formed on the interlayer insulating film so as to cover the opening. The interlayer insulating film contains nitrides in an amount larger than that in the gate insulating film, and the semiconductor film includes a microcrystalline semiconductor film or a polycrystalline semiconductor film formed on semiconductor crystalline nuclei which are formed on the gate insulating film and the interlayer insulating film and contain at least Ge.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: One object is to provide a transistor including an oxide semiconductor film which is used for the pixel portion of a display device and has high reliability. A display device has a first gate electrode; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode over the oxide semiconductor film; a second gate insulating film over the source electrode, the drain electrode and the oxide semiconductor film; a second gate electrode over the second gate insulating film; an organic resin film having flatness over the second gate insulating film; a pixel electrode over the organic resin film having flatness, wherein the concentration of hydrogen atoms contained in the oxide semiconductor film and measured by secondary ion mass spectrometry is less than 1×1016 cm?3.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: A memory cell includes a bottom electrode, a top electrode and a memory element switchable between electrical property states by the application of energy. The bottom element includes lower and upper parts. The upper part has a generally ring-shaped upper end surrounding a non-conductive central region. The lateral dimension of the lower part is longer, for example twice as long, than the lateral dimension of the ring-shaped upper end. The lower part is a non-perforated structure. The memory element is positioned between and in electrical contact with the top electrode and the ring-shaped upper end of the second part of the bottom electrode. In some examples the ring-shaped upper end has a wall thickness at the memory element of 2-10 nm. A manufacturing method is also discussed.

Abstract: The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart.

Abstract: A thin film transistor device and method of making the same are provided. The thin film transistor device includes a crystalline semiconductor layer and a patterned heavily doped semiconductor layer. The patterned heavily doped semiconductor layer includes a first heavily doped semiconductor layer and a second heavily doped semiconductor layer. The first heavily doped semiconductor layer covers a first side surface and a portion of a top surface of the crystalline semiconductor layer; the second heavily doped semiconductor layer covers a second side surface and a portion of the top surface of the crystalline semiconductor layer.

Abstract: A process for forming at least one transistor on a substrate is described. The substrate comprises a polyimide and a nanoscopic filler. The polyimide is derived substantially or wholly from rigid rod monomers and the nanoscopic filler has an aspect ratio of at least 3:1. The substrates of the present disclosure are particularly well suited for thin film transistor applications, due at least in part to high resistance to hygroscopic expansion and relatively high levels of thermal and dimensional stability.

Abstract: An active matrix substrate (101A) comprises a transparent substrate (10), a wiring formed on the transparent substrate (such as LG, LD, LP, L1, and L2), a transparent semiconductor layer (44) that covers at least a part of the wiring, and a transparent insulating film that covers at least a part of the wiring and of the transparent semiconductor layer. The wiring comprises a first metal wiring (41M) serving as a main wiring and a transparent wiring (such as 41, 42, and 43) that branches from the main wiring and serves as a sub-wiring. At least a part of the first metal wiring serving as the main wiring is formed by using a material that has a higher conductivity than that of a material for a wiring serving as the sub-wiring.

Abstract: A flexible display substrate includes: a thin film transistor on the flexible substrate, the thin film transistor including a gate electrode, a gate insulating layer insulating the gate electrode, a channel layer on the gate insulating layer, a source electrode connected with the channel layer, and a drain electrode connected with the channel layer; a first stress absorbing layer below the thin film transistor; a first protection layer on the first stress absorbing layer; a second stress absorbing layer on the thin film transistor; a second protection layer on the second stress absorbing layer; and a pixel electrode on the second protection layer, the pixel electrode being connected with the drain electrode.

Abstract: Provided is a method of promoting a deposition of semiconductor crystal nuclei on an insulating film such as a silicon oxide film even at a low temperature of 450° C. or lower in a reactive thermal CVD method. As one means thereof, a first semiconductor film is formed on an insulating substrate, and then semiconductor crystal nuclei are formed on parts of the first semiconductor film and simultaneously the first semiconductor film other than that in forming regions of the semiconductor crystal nuclei and their peripheries is removed by etching. Thereafter, a second semiconductor film is formed with using the semiconductor crystal nuclei as seeds.

Abstract: A method of making a crystalline film includes providing a film comprising seed grains of a selected crystallographic surface orientation on a substrate; irradiating the film using a pulsed light source to provide pulsed melting of the film under conditions that provide a mixed liquid/solid phase and allowing the mixed solid/liquid phase to solidify under conditions that provide a textured polycrystalline layer having the selected surface orientation. One or more irradiation treatments may be used. The film is suitable for use in solar cells.

Abstract: A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel thereof. The Si thin film includes a polycrystal where a plurality of narrow, rectangular crystal grains are arranged. A surface of the polycrystal is flat at grain boundaries thereof. Also, an average film thickness of the boundaries of crystals of the Si thin film ranges from 90 to 110% of an intra-grain average film thickness.

Abstract: The disclosed subject matter generally relates a method of irradiating a large area thin film with a pulsed light source. In some embodiments, the disclosed subject matter particularly relates to utilizing flash lamp annealing in combination with patterning techniques for making thin film devices. The flash lamp annealing can trigger lateral growth crystallization or explosive crystallization in large area thin films. In some embodiments, capping layers or proximity masks can be used in conjunction with the flash lamp annealing.

Abstract: Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.

Abstract: A semiconductor device which comprises a channel layer formed from a semiconductor channel component material in the form of crystalline micro particles, micro rods, crystalline nano particles, or nano rods, and doped with a semiconductor dopant.

Abstract: This semiconductor device includes a substrate, an underlayer formed on a main surface of the substrate, a first semiconductor layer and a second semiconductor layer. Unstrained lattice constants of the underlayer and the second semiconductor layer in a second direction are larger than a lattice constant of the substrate in the second direction in an unstrained state. Lattice constants of the underlayer and the second semiconductor layer in the second direction in a state of being formed on the main surface are larger than the lattice constant of the substrate in the second direction.

Abstract: A switching device with a solid electrolyte layer includes: a substrate; a lower electrode formed over the substrate; a solid electrolyte layer disposed over the lower electrode; and an upper electrode formed over the solid electrolyte layer.

Abstract: Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing a seed layer on a base substrate, covering the seed layer with an amorphous/poly material, and heating the seed layer/material to transform the material into crystalline form.

Abstract: Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes.

Abstract: A TFT array panel and a manufacturing method thereof, The TFT array panel includes an insulation substrate, a plurality of gate lines, a plurality of first dummy wiring lines, a gate insulating layer, and a plurality of data lines. The insulation substrate has a display area for displaying an image and a peripheral area outside the display area. The plurality of gate lines are formed in the display area and in a portion of the peripheral area. The plurality of first dummy wiring lines are insulated from the gate lines and formed in the peripheral area. The gate insulating later is formed on the gate lines and the first dummy wiring lines, and has at least one contact hole exposing at least lateral end portions of the first dummy wiring lines.

Abstract: A method of crystallizing an amorphous semiconductor film, the method comprising the steps of: forming a gate electrode on a transparent insulating substrate; forming a gate insulating film on the transparent insulating substrate and on an upper part of the gate electrode; forming an amorphous semiconductor film on the gate insulating film; forming a light-transmissive insulating film on the amorphous semiconductor film; forming a metal film having an opening on the light-transmissive insulating film; irradiating laser light onto both a region of the light-transmissive insulating film exposed by the opening and the metal film, which is used as a mask for shielding the laser light; and performing laser annealing to make the laser light to be absorbed through the light-transmissive insulating film into a region of the amorphous semiconductor film exposed by the opening, so that the amorphous semiconductor film is heated and converted to a crystalline semiconductor film.

Abstract: An organic light emitting diode display includes a thin film transistor on a substrate (1). The thin film transistor includes a gate electrode (2), a gate insulating film (3) that covers the gate electrode (2), a first semiconductor film (4) provided on the gate insulating film (3), a second semiconductor film (5) provided on the first semiconductor film (4), a back channel protection insulating film (7) and an ohmic contact film (8) provided on the second semiconductor film (5), and source/drain electrodes (9). A crystallinity of the first semiconductor film (4) is higher than that of the second semiconductor film (5). The back channel protection insulating film (7) is formed as one of an organic insulating film and an organic/inorganic hybrid insulating film. The thin film transistor has excellent off-state characteristics, swing characteristics, and saturation characteristics.

Abstract: To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.

Abstract: A MEMS device has a first member that is movable relative to a second member. At least one of the first member and the second member has exposed silicon carbide with a water contact angle of greater than about 70 degrees.

Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

Abstract: A laser method is provided for minimizing variations in transistor threshold voltages. The method supplies a wafer with a laser-crystallized active semiconductor film having a top surface with a first surface roughness. The method laser anneals the active semiconductor film, and in response to the laser annealing, melts the top surface of the active semiconductor film. The result is a top surface with a second roughness, less than the first roughness. More explicitly, the wafer active semiconductor film is crystallized using a laser with a first fluence, and then laser annealed with a second fluence, less than the first fluence. As compared with complementary metal-oxide-semiconductor field-effect (CMOSFET) thin-film transistor (TFT) structures formed in unprocessed regions of the active semiconductor film, the TFT threshold voltage standard deviation for TFTs in laser annealed portions of the active film are 60% less for n-channel and 30% less for p-channel TFTs.

Abstract: A semiconductor structure is described, including a semiconductor substrate and a semiconductor layer disposed on the semiconductor substrate. The semiconductor layer is both compositionally graded and structurally graded. Specifically, the semiconductor layer is compositionally graded through its thickness from substantially intrinsic at the interface with the substrate to substantially doped at an opposite surface. Further, the semiconductor layer is structurally graded through its thickness from substantially crystalline at the interface with the substrate to substantially amorphous at the opposite surface. Related methods are also described.

Abstract: Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InxGayAl1-x-yN alloy. The lattice parameter of the InxGayAl1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a?)=?2(a) or (a?)=(a)/?2. The semiconductor alloy may be prepared to have a selected band gap.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: Provided is a sensor having a high sensitivity and a high degree of freedom of layout by reducing constrictions of the channel shape, the reaction field area, and the position. Provided is also a method for manufacturing the sensor. The sensor (10) includes: a source electrode (15), a drain electrode, (14), and a gate electrode (13) arranged on silicon oxide film (12a, 12b); a channel (16) arranged on the silicon oxide films (12a, 12b) and electrically connected to the source electrode (15) and the drain electrode (14); and a reaction field (20) arranged on the silicon oxide films (12a, 12b). The reaction field (20) is formed at a position on the silicon oxide film (12a), the position being different from a position for the channel (16). With this configuration, it is possible to independently select the shape of the channel (16) and the area of the reaction field (20). This enables the sensor (10) to have a high measurement sensitivity and a high degree of freedom of layout.

Abstract: An organic light emitting diode (OLED) display device having a pixel area and a pad area. The pad area includes a silicon layer pattern arranged on the substrate, an insulating layer arranged on the silicon layer pattern, an interconnection layer arranged on the insulating layer, and a protective layer surrounding an edge of the interconnection layer and having an opening exposing the interconnection layer. Since a surface area of the interconnection layer is increased due to a roughness of the underlying polycrystalline silicon layer pattern in the pad area, resulting in increased contact area and reduced contact resistance between parts configured to operate a flat panel display device and the interconnection layer is increased.

Abstract: A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: An array substrate for a liquid crystal display device includes a gate line and a data line crossing each other on a substrate to define a pixel region, an insulating layer between the gate line and the data line, a gate electrode extending from the gate line, and a transistor in the pixel region having an active layer on the insulating layer, ohmic contact layers of a first material that are adjacent to ends of the active layer, buffer layers of a second material, which is different from the first material, on the ohmic contact layers, a source electrode contacting one of the buffer layers and a drain electrode contacting another one of the buffer layers, wherein the active layer is in an island shape over the gate electrode and within a boundary defined by a perimeter of the gate electrode.

Abstract: The present invention provides a semiconductor device which can reduce Ion defects due to reduction in an on-current. A semiconductor device of the present invention comprises: a substrate; a thin film transistor including a crystalline semiconductor layer which has a channel region and a source/drain region; and a wiring connected to the source/drain region. The thin film transistor and the wiring are disposed on the substrate. The crystalline semiconductor layer further has a low-impurity-concentration region which has a lower impurity concentration than that of the source/drain region and a contacting portion contacting with the wiring. The low-impurity-concentration region is disposed adjacent to the source/drain region except a region on a channel-region side of the source/drain region.

Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.

Abstract: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through the channel region varies at different points along the width direction, e.g., to give an improvement in the distortion characteristics of the transistor.

Abstract: A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.

Abstract: A method of forming a microstructure body and a semiconductor element for controlling the microstructure body over the same substrate to reduce manufacturing cost, for mass-production of micromachines having a microstructure. In manufacturing a micromachine, a sacrifice layer is formed using a mask material for forming a pattern of a film, and removal of the mask in a region for forming a semiconductor element and removal of the sacrifice layer and the mask in a region for forming a microstructure body are performed by the same step. Specifically, a manufacturing method of a micro-electro-mechanical device is provided wherein a sacrifice layer is selectively formed over an insulating substrate, a semiconductor layer is formed to cover the sacrifice layer, a mask is formed over the semiconductor layer, the semiconductor layer is etched using the mask, and the mask and the sacrifice layer are removed by the same step.

Abstract: A gallium nitride based field effect transistor having good current hysteresis characteristics in which forward gate leakage can be reduced. In a gallium nitride-based field effect transistor (100) having a gate insulation film (108), part or all of a material constituting the gate insulation film (108) is a dielectric material having a relative dielectric constant of 9-22, and a semiconductor crystal layer A (104) in contact with the gate insulation film (108) and a semiconductor crystal layer B (103) in the vicinity of the semiconductor crystal layer A (104) and having a larger electron affinity than the semiconductor crystal layer A (104) constitute a hetero junction. A hafnium oxide such as HfO2, HfAlO, HfAlON or HfSiO is preferably contained, at least partially, in the material constituting the gate insulation film (108).

Abstract: Problems exist in areas such as image visibility, endurance of the device, precision, miniaturization, and electric power consumption in an information device having a conventional resistive film method or optical method pen input function. Both EL elements and photoelectric conversion elements are arranged in each pixel of a display device in an information device of the present invention having a pen input function. Information input is performed by the input of light to the photoelectric conversion elements in accordance with a pen that reflects light by a pen tip. An information device with a pen input function, capable of displaying a clear image without loss of brightness in the displayed image, having superior endurance, capable of being miniaturized, and having good precision can thus be obtained.

Abstract: The present invention is a silicon single crystal wafer grown by the Czochralski method, the silicon single crystal wafer in which an wafer entire plane is an N region located outside OSFs which are generated in the form of a ring when thermal oxidation treatment is performed and contains no defect region detected by the RIE process. As a result, a silicon single crystal wafer which belongs to none of a vacancy-rich V region, an OSF region, a Dn region in an Nv region, the Dn region in which a defect detected by the Cu deposition process is generated, and an interstitial silicon-rich I region and can improve the TDDB characteristic which is the time dependent breakdown characteristic of an oxide film more reliably than a known silicon single crystal wafer is provided, and the silicon single crystal wafer is provided under stable production conditions.

Abstract: A display panel by which variation in dispersion density of spacers that contribute to definition of a cell gap therebetween is reduced so as to make the cell gap uniform, an array substrate, a color filter substrate, and a method for producing a display panel. The display panel is configured such that one of an array substrate 10 and a color filter substrate 30 that are opposed to each other leaving a given cell gap therebetween includes a concave portion 161, the other substrate includes a convex portion 361 that is opposed to the concave portion, and spacers are interposed between a bottom surface of the concave portion and a top surface of the convex portion.