Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.

Abstract: According to one embodiment, a power semiconductor device includes a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type periodically disposed repeatedly along a surface of the first semiconductor layer on a first semiconductor layer of the first conductivity type. A first main electrode is provided to electrically connect to the first semiconductor layer. A fourth semiconductor layer of the second conductivity type is provided to connect to the third semiconductor layer. Fifth semiconductor layers of the first conductivity type are selectively provided in the fourth semiconductor layer surface. A second main electrode is provided on a surface of the fourth and fifth semiconductor layers. A control electrode is provided on a surface of the fourth, fifth, and second semiconductor layers via a gate insulating film. First insulating films are provided by filling a trench made in the second semiconductor layer.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

Abstract: One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.

Abstract: A semiconductor device includes an active region formed in a substrate; an isolation structure formed to surround the active region; and one or more dummy regions formed between the active region and the isolation structure to extend integrally from the active region.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 ?-?m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film 11 is of the conductivity type opposite to that of the transistor (p-type in the case of an n-type MOS transistor whereas n-type in the case of a p-type MOS transistor). In this way, the mobility in a semiconductor device including a semiconductor film having a heterojunction structure with a compression strain structure is increased, thereby improving the transistor characteristics and reliability of the device.

Abstract: A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor portion overlying the underlying doped region, wherein the semiconductor portion has a primary surface spaced apart from the underlying doped region. The process can further include forming a vertically-oriented conductive region extending from the primary surface towards the underlying doped region, forming a horizontally-oriented doped region adjacent to the primary surface, and forming a conductive electrode over, spaced-apart from, and electrically insulated from the vertically-oriented doped region. The process can still further include forming a gate electrode after forming the conductive electrode. The electronic device can include a transistor that includes the underlying doped region, the vertically-oriented conductive region, the horizontally-oriented doped region, and the gate electrode.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 m?*nC.

Abstract: In a semiconductor film having a heterojunction structure, for example a semiconductor film (11) including a SiGe layer (2) and a Si layer (3) formed on the SiGe layer (2), impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer (2) becomes higher than that in the upper, Si layer (3) by exploiting the fact that there is a difference between the SiGe layer (2) and the Si layer (3) in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film 11 is of the conductivity type opposite to that of the transistor (p-type in the case of an n-type MOS transistor whereas n-type in the case of a p-type MOS transistor). In this way, the mobility in a semiconductor device including a semiconductor film having a heterojunction structure with a compression strain structure is increased, thereby improving the transistor characteristics and reliability of the device.

Abstract: A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques.

Abstract: A semiconductor device includes a gate electrode formed through a gate insulating film provided on a first impurity region and a drift layer, and this gate electrode consists of two regions including a first conductivity type second impurity region opposed to the first impurity region and a third impurity region capable of forming a depletion layer.

Abstract: A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region. The process can also include forming a vertically-oriented conductive region extending from the primary surface to the underlying doped region, and forming a horizontally-oriented doped region adjacent to the primary surface. In a finished form of the electronic device, the horizontally-oriented doped region extends further in a lateral direction toward a region where a source region has been or will be formed, as compared to the vertically-oriented conductive region. The electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, and the horizontally-oriented doped region.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other; a source region and a drain region disposed at sides of the floating gate device; an insulation layer disposed on the floating gate device and the source region, and a polysilicon line extending in the word line direction and connected to the drain region.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 ?-?m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

Abstract: An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 m?*nC.

Abstract: A power semiconductor device includes: a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on a first semiconductor layer and alternately arranged along at least one direction parallel to an upper face of the first semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively formed in an upper face of the second and third semiconductor layers; and a control electrode formed above the second, third and fourth semiconductor layers via a gate insulating film. The control electrode includes: first portions periodically arranged along a first direction selected from arranging directions of the third semiconductor layer, the third semiconductor layer has a shortest arrangement period in the first direction, and second portions periodically arranged along a second direction, the second direction being parallel to the upper face of the first semiconductor layer and crossing the first direction.

Abstract: The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices can be formed in a well on a substrate where isolation trenches surround one or more devices to create storage regions (floating wells) that is capable of holding a charge. Depending on the charge in the storage region (floating well), it can represent information. The semiconductor devices of the present invention can be manufactured using the standard process of manufacturing (bulk cmos processing).

Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.

Abstract: A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

Abstract: A semiconductor device includes a semiconductor substrate, a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate, a gate electrode formed on the channel region via a gate insulating film, a pair of source/drain electrodes of a second conductivity type provided on both sides of the gate electrode, metallic compound layers formed on the source/drain electrodes, stress application layers located under the respective source and drain electrodes and each having a crystal structure whose intrinsic lattice spacing is different from lattice spacing inherent in a substance constituting the source/drain electrodes, and first buried insulating regions disposed under the respective stress application layers.

Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

Abstract: A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer are sequentially formed over the substrate. A floating gate is defined in the memory cell region and the top layer and the first conductive layer of the high voltage circuit region are removed. The exposed silicon oxide layer is thickened. Thereafter, the top layer is removed and then a barrier layer is formed on the exposed surface of the floating gate. A second conductor layer is formed over the substrate, and then a gate is defined in the high voltage circuit region and a control gate is defined in the memory cell region.

Abstract: A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.

Abstract: There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a device isolation insulation film filling the device isolation trench. At least a surface part of the device isolation insulation film is formed of an HF-resistant film.

Abstract: A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.

Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined death for realizing defined channel connection regions.

Abstract: In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided on the semiconductor layer, a gate electrode provided on the gate insulating layer, and an impurity region that constitutes a source region or a drain region provided in the semiconductor layer; wherein a removed region made by removing the etching stopper film is provided in at least part of an area that is located outside the gate insulating layer and above an area at a position other than a position sandwiched by the gate insulating layer and the impurity region.

Abstract: This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.

Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.

Abstract: A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.

Abstract: In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an additional n-region next to the drain or an additional floating p-region next to the drain.

Abstract: A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.