Isolation By Dielectric Regions (epo) Patents (Class 257/E29.02)
  • Patent number: 8994103
    Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Lin Chen, Tseng-Hsun Liu, Kuan-Yu Chen, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang
  • Patent number: 8981519
    Abstract: A semiconductor substrate (41) includes an insulating substrate (30), a plurality of semiconductor thin films (46) which are arranged on the insulating substrate (30) to be separated from each other, and a conductive film (33) which is arranged between the semiconductor thin films (46). Therefore, it is possible to uniformly thin the film thickness of each of the semiconductor thin films.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 17, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 8969869
    Abstract: An integrated circuit wafer and integrated circuit dice are provided. The integrated circuit wafer includes a wafer substrate, a plurality of integrated circuits, a plurality of test-keys, an isolation film, and a plurality of ditches. The integrated circuits are disposed on the wafer substrate in matrix. The test-keys are respectively disposed between the adjacent integrated circuits. The isolation film covers at least one side of the integrated circuits on the wafer substrate. The ditches extend downwardly from the surface of the isolation film and are disposed between the integrated circuit and the adjacent test-key. The integrated circuit die includes a wafer substrate, an integrated circuit disposed on the wafer substrate, and an isolation film covering at least one side of the integrated circuit on the wafer substrate, wherein the side walls of the wafer substrate and the isolation film are respectively smooth walls. The side wall of the wafer substrate is substantially vertical.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: March 3, 2015
    Assignee: Raydium Semiconductor Corporation
    Inventor: Yao-Sheng Huang
  • Patent number: 8963280
    Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8963282
    Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: February 24, 2015
    Assignee: Nanya Technology Corp.
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8952484
    Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: February 10, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
  • Patent number: 8946853
    Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
  • Patent number: 8946908
    Abstract: Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8907382
    Abstract: A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: December 9, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jui-Chun Chang
  • Patent number: 8907405
    Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Reinaldo A. Vega, Hongwen Yan
  • Patent number: 8901716
    Abstract: An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventor: James C. Matayabas, Jr.
  • Patent number: 8890257
    Abstract: Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8852996
    Abstract: Provided are carbon doped resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming thereof. Carbon doping of metal containing materials creates defects in these materials that allow forming and breaking conductive paths as evidenced by resistive switching. Relative to many conventional dopants, carbon has a lower diffusivity in many suitable base materials. As such, these carbon doped materials exhibit structural stability and consistent resistive switching over many operating cycles. Resistive switching layers may include as much as 30 atomic percent of carbon, making the dopant control relatively simple and flexible. Furthermore, carbon doping has acceptor characteristics resulting in a high resistivity and low switching currents, which are very desirable for ReRAM applications. Carbon doped metal containing layer may be formed from metalorganic precursors at temperatures below saturation ranges of atomic layer deposition.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 7, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8853662
    Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 8846492
    Abstract: An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang
  • Patent number: 8847189
    Abstract: A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventor: Wataru Ootsuka
  • Patent number: 8829622
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
  • Patent number: 8828840
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Chinese Academy of Sciences, Institute of Microelectronics
    Inventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
  • Patent number: 8829643
    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Zailong Bian, Janos Fucsko
  • Patent number: 8816470
    Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8816471
    Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 26, 2014
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8785989
    Abstract: The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Lucien J. Bissey, William A. Stanton
  • Patent number: 8772904
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
  • Patent number: 8766355
    Abstract: A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kak Lee, Hee-don Hwang
  • Patent number: 8742536
    Abstract: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realization of MEMS structures of SOI wafers. A reliable dielectric insulation of adjacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches. The end portions of the trench fill that are freed from the surrounding silicon by etching are free of conductive not completely removed silicon strips in the recess including the active sensor structure. This is accomplished by slanted wall of isolation trenches. Additionally, the trench fill should be removable at the transition area in an efficient manner. The technological realization does not require specific additional process steps.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: June 3, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Karlheinz Freywald, Gisbert Hoelzer
  • Patent number: 8741734
    Abstract: A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Bum Kim
  • Patent number: 8710619
    Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Kawamata, Atsushi Tachigami, Kazuya Horie, Tatsuya Shiromoto, Tetsuya Nitta, Hironori Shimizu
  • Patent number: 8698274
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
  • Patent number: 8692352
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: 8692353
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
  • Patent number: 8686534
    Abstract: A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: April 1, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Chao Zhao, Qingqing Liang
  • Patent number: 8686533
    Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chun Wang, Tzu-Hsuan Hsu
  • Patent number: 8673699
    Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Bala S. Haran, Pranita Kulkarni, Amlan Majumdar, Stefan Schmitz
  • Patent number: 8664742
    Abstract: An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8664080
    Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Tani, Hiroshi Yamasaki, Kentaro Takahashi, Lily Springer
  • Patent number: 8659114
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench formed in an element isolating area of the semiconductor substrate, and a silicon oxide film that is embedded in the trench and contains an alkali metal element or alkali earth metal element.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8643104
    Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Shan Liao, An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang
  • Patent number: 8643138
    Abstract: A high breakdown voltage integrated circuit isolator device communicates a digital signal from a signal input on one semiconductor die to a signal output on another semiconductor die while providing high voltage isolation between the signal input and the signal output. Each die may include a respective capacitive isolation barrier structure that couple together via a bonding wire between combined top metal/bonding pads of the capacitive isolation barrier structures.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 4, 2014
    Assignee: Silicon Laboratories Inc.
    Inventor: Zhiwei Dong
  • Patent number: 8643034
    Abstract: An optoelectronic semiconductor body comprises a semiconductor layer sequence which is subdivided into at least two electrically isolated subsegments. The semiconductor layer sequence has an active layer in each subarea. Furthermore, at least three electrical contact pads are provided. A first line level makes contact with a first of the at least two subsegments and with the first contact pad. A second line level makes contact with the second of the at least two subsegments and with a second contact pad. A third line level connects the two subsegments to one another and makes contact with the third contact pad. Furthermore, the line levels are each arranged opposite a first main face, wherein the first main face is intended to emit electromagnetic radiation that is produced.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: February 4, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Engl, Frank Singer, Patrick Rode, Lutz Hoeppel, Martin Strassburg
  • Patent number: 8637934
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
  • Publication number: 20140015092
    Abstract: A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael V. Aquilino, Xiang Hu, Daniel J. Jaeger, Byeong Y. Kim, Yong M. Lee, Ying Li, Reinaldo A. Vega
  • Patent number: 8629559
    Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
  • Publication number: 20130341754
    Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Applicant: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kulkarni, Arvind Kumar, Shom Ponoth
  • Patent number: 8614490
    Abstract: A semiconductor device of the present invention includes: transistor Tr1 arranged on a semiconductor substrate; transistor Tr2 arranged such that a carrier drift direction thereof viewed on the semiconductor substrate is identical to a carrier drift direction of transistor Tr1; diffusion layer 51c connecting diffusion layers 51a and 51b on carrier supply sides of transistors Tr1 and Tr2; and contact plug 61 that is connected to a surface of diffusion layers 51a and 51b on the carrier supply sides of transistors Tr1 and Tr2 or that is connected to a surface of diffusion layer 51c connecting the diffusion layers to each other, and that supplies diffusion layers 51a and 51b with electricity.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: December 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Masaki Yoshimura
  • Patent number: 8614137
    Abstract: The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Kemerer, James S. Nakos, Steven M. Shank
  • Patent number: 8614482
    Abstract: A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 24, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130334650
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
  • Patent number: 8610239
    Abstract: A semiconductor device including an isolation layer structure including a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate including an active region in which the first trench is not formed and a field region including the first trench, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region; a well region at a portion of the active region adjacent to lower portions of the doped polysilicon layer pattern and being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to upper portions of the doped polysilicon layer pattern and being doped with fourth impurities of the first conductivity type.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Uk Han, Satoru Yamada
  • Publication number: 20130328159
    Abstract: Methods and structures are provided for implementing independently voltage controlled isolated silicon regions under a buried oxide layer for biasing field effect transistors above the buried oxide layer on Silicon-on-Insulator (SOI) wafers. Using a bonded-wafer technique, a first bulk substrate wafer is bonded with a second wafer providing a buried oxide (BOX) layer under a transistor silicon layer creating an SOI wafer. An independently voltage controlled isolated silicon region is created in the created SOI wafer beneath the BOX layer. The transistor silicon layer is polished to a desired thickness, and normal processing is continued with transistors and desired circuits placed over the isolated silicon region. A contact is formed through the transistor silicon layer and BOX layer to the isolated silicon region for connecting the independently voltage controlled isolated silicon region to a voltage.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Publication number: 20130320487
    Abstract: A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 5, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze