Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

Abstract: A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged.

Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.

Abstract: In one embodiment, a bidirectional voltage-regulator diode includes first to fifth semiconductor layers formed on an inner surface of a first recess formed in a semiconductor substrate of an N-type in the order. The first semiconductor layer of the N-type has a first impurity concentration lower than an impurity concentration of the semiconductor substrate. The second semiconductor layer of a P-type has a second impurity concentration. The third semiconductor layer of the P-type has a third impurity concentration higher than the second impurity concentration. The fourth semiconductor layer of the P-type has a fourth impurity concentration lower than the third impurity concentration. The fifth semiconductor layer of the N-type has a fifth impurity concentration.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.

Abstract: An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.

Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

Abstract: A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4).