Noninterconnected Multiemitter Structures (epo) Patents (Class 257/E29.032)
  • Patent number: 10217792
    Abstract: The invention relates to a method for producing an optoelectronic semiconductor chip (1). A semiconductor layer sequence (3) is provided, comprising a first semiconductor layer (3a) and a second semiconductor layer (3b). Furthermore, a first contact layer (5a) is provided which extends laterally along the first semiconductor layer (3a) and electrically contacts same. A third semiconductor layer (7) is applied onto a first contact layer (5a) face facing away from the semiconductor layer sequence (3). A recess (8) is formed which extends through the third semiconductor layer (7), the first contact layer (5a), and the first semiconductor layer (3a) into the second semiconductor layer (3b). A passivation layer (9) is applied onto a third semiconductor layer (7) face facing away from the semiconductor layer sequence (3). At least one first (9a) and at least one second passage opening (9b, 9c) are formed in the passivation layer (9).
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 26, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Korbinian Perzlmaier, Lutz Hoeppel
  • Patent number: 10181494
    Abstract: The invention relates to a method for producing an optoelectronic semiconductor chip (1). A semiconductor layer sequence (3) is provided, comprising a first semiconductor layer (3a) and a second semiconductor layer (3b). Furthermore, a first contact layer (5a) is provided which extends laterally along the first semiconductor layer (3a) and electrically contacts same. A third semiconductor layer (7) is applied onto a first contact layer (5a) face facing away from the semiconductor layer sequence (3). A recess (8) is formed which extends through the third semiconductor layer (7), the first contact layer (5a), and the first semiconductor layer (3a) into the second semiconductor layer (3b). A passivation layer (9) is applied onto a third semiconductor layer (7) face facing away from the semiconductor layer sequence (3). At least one first (9a) and at least one second passage opening (9b, 9c) are formed in the passivation layer (9).
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 15, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Korbinian Perzlmaier, Lutz Hoeppel
  • Patent number: 7897497
    Abstract: A light-generating semiconductor region is grown by epitaxy on a silicon substrate. The light-generating semiconductor region is a lamination of layers of semiconducting nitrides containing a Group III element or elements. The silicon substrate has a p-type impurity-diffused layer formed therein by thermal diffusion of the Group III element or elements from the light-generating semiconductor region as a secondary product of the epitaxial growth of this region on the substrate. The p-type impurity-diffused layer is utilized as a part of overvoltage protector diodes which are serially interconnected with each other and in parallel with the LED section of the device between a pair of electrodes.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: March 1, 2011
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Yasuhiro Kamii, Arei Niwa, Junji Sato, Mikio Tazima
  • Patent number: 7859082
    Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: December 28, 2010
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher