Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.

Abstract: The integrated capacitor structure comprises a first branch with a first capacitor (60) and a second branch with a second capacitor (70). The second capacitor (70) has a higher capacitance density and a lower breakdown voltage than the first capacitor (60). The first branch has a shorter RC time constant than the second branch, such that a voltage peak will substantially follow the first branch. This first capacitor (60) has a sufficient capacity to store the charge of the voltage peak. In one embodiment, the second capacitor (70) is a stacked capacitor. The structure is suitable for ESD-protection and may, to this end, additionally comprise diodes (21) and resistors (22).

Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.

Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.

Abstract: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.

Abstract: The present invention relates to a microelectronic device having a bipolar epitaxial structure that provides at least one bipolar transistor element formed over at least one field effect transistor (FET) epitaxial structure that provides at least one FET element. The epitaxial structures are separated with at least one separation layer. Additional embodiments of the present invention may use different epitaxial layers, epitaxial sub-layers, metallization layers, isolation layers, layer materials, doping materials, isolation materials, implant materials, or any combination thereof.

Abstract: For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then indiffused into the semiconductor substrate from the dielectric layer serving as a dopant repository. This gives rise to a low-resistance region with which the extrinsic base can be defined carefully.

Abstract: A bipolar transistor includes a base layer design and a method for fabricating such a bipolar transistor that employ a built-in accelerating field focused on a base region adjacent to a collector, where minority carrier transport is otherwise retarded. The accelerating field of the base layer includes on average, a relatively low p-doping level in a first region proximate to the collector and a relatively high p-doping level in a second region proximate to an emitter. Alternatively, the accelerating field can be derived from band gap grading, wherein the grade of band gap in the first region is greater than the grade of band gap in the second region, and the average band gap of the first region is lower than that of the second region.

Abstract: A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material is deposited. The first semiconductor layer is partially exposed by partial removal of the second layer. A first reaction layer is deposited that, together with the first semiconductor layer forms reaction products, which are selectively removable with respect to adjacent regions. Remaining material of the first reaction layer that has not reacted with the material of the first semiconductor layer is removed. A second reaction layer is deposited that, with the first semiconductor layer, forms a low-resistivity compound. Remaining material of the second reaction layer that has not reacted with the material of the first semiconductor layer is removed.

Abstract: A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a heterostructure bipolar transistor (HBT) including: a substrate; a monocrystalline emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; a monocrystalline silicon germanium (SiGe) intrinsic base extending over each isolation region; and a monocrystalline silicon extrinsic base. A method may include forming the intrinsic and extrinsic base and the emitter as monocrystalline, with the extrinsic base (and emitter) formed in a self-aligned fashion utilizing selective-epitaxial growth on porous silicon. As a result, some mask levels can be omitted, making this an inexpensive alternative to conventional processing.

Abstract: A base structure for high performance Silicon Germanium (SiGe) based heterojunction bipolar transistors (HBTs) with arsenic atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas or hydrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe spacer layer. The surface of the final silicon cap layer is preferably etched to remove most of the arsenic. The resulting SiGe HBT with an arsenic ALD layer is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.

Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.

Abstract: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have enhanced characteristics.

Abstract: In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.

Abstract: A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are epitaxially grown single crystal silicon that is doped during the growth.