Of Lateral Transistors (epo) Patents (Class 257/E29.045)
  • Patent number: 8962436
    Abstract: A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Ghavam G. Shahidi, Jeng-Bang Yau
  • Patent number: 8569866
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 29, 2013
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8410572
    Abstract: A base contact connection, an emitter structure and a collector structure are arranged on an n-layer, which can be provided for additional npn transistors. The collector structure is arranged laterally to the emitter structure and at least one of the emitter and collector comprises a Schottky contact on a surface area of the n-layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 2, 2013
    Assignee: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Patent number: 7705426
    Abstract: The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventor: Steven Voldman