With Nonplanar Gate Structure (epo) Patents (Class 257/E29.067)
  • Patent number: 8847233
    Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Junichi Koezuka, Shunpei Yamazaki
  • Patent number: 8835261
    Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Patent number: 8378414
    Abstract: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 19, 2013
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Volker Dudek, Michael Graf
  • Patent number: 8293591
    Abstract: A field effect transistor for detecting an analyte having a thiol group includes a substrate, a source region and a drain region formed apart from each other on the substrate, the source region and the drain region being doped such that a polarity of the source and drain region is opposite to a polarity of the substrate, a channel region disposed between the source region and the drain region, an insulating layer formed of an electrically insulating material and disposed on the channel region, a gold layer disposed on the insulating layer and a reference electrode disposed apart from the gold layer.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeo-young Shim, Kyu-tae Yoo, Kyu-sang Lee, Won-seok Chung, Yeon-ja Cho, Chang-eun Yoo
  • Patent number: 8274095
    Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 25, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshiaki Hisamoto
  • Patent number: 8269283
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
  • Patent number: 8148217
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 8049273
    Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.
    Type: Grant
    Filed: February 15, 2009
    Date of Patent: November 1, 2011
    Assignee: Anpec Electronics Corporation
    Inventors: Wei-Chieh Lin, Ho-Tai Chen, Li-Cheng Lin, Jen-Hao Yeh, Hsin-Yen Chiu, Hsin-Yu Hsu, Shih-Chieh Hung
  • Patent number: 8043904
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 8017974
    Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: September 13, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshiaki Hisamoto
  • Patent number: 7982265
    Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: July 19, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Alan Elbanhawy, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Christopher B. Kocon
  • Patent number: 7888733
    Abstract: A power semiconductor having a first, second, third, and fourth semiconductor layer on top of each other, two trench gates parallel and adjacent to each other, each having a trench in the fourth semiconductor layer with the a trench bottom portion reaching into the third semiconductor layer, a gate insulation film lining the trench, and a gate electrode filling the trench being lined with the gate insulation film, two first semiconductor region regions provided contiguously bordering on one side of each of the two trench gates, located at the outer sides of each of the two adjacent trench gates, and located in the top side of the fourth semiconductor layer, a first main electrode on the fourth semiconductor layer, and a second main electrode provided on a bottom of the first semiconductor layer.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: February 15, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Eisuke Suekawa
  • Patent number: 7692222
    Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 6, 2010
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Robert B. Hallock
  • Patent number: 7662679
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: February 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 7456484
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: November 25, 2008
    Assignee: Denso Corporation
    Inventors: Yoshihiko Ozeki, Norihito Tokura, Yukio Tsuzuki
  • Patent number: 7345339
    Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: March 18, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Mikimasa Suzuki, Yoshiyuki Hattori