In Different Semiconductor Regions (e.g., Heterojunctions) (epo) Patents (Class 257/E29.081)
  • Patent number: 10563424
    Abstract: A dual authentication system of an electronic locking device using an electronic key according to an exemplary embodiment of the present invention includes a receiving unit that receives UID data pre-stored in the electronic key and encoding data generated by an input of a button provided in the electronic key, when a terminal portion provided in a key head of the electronic key is in electrical contact with a data communication unit of the electronic locking device; an authentication unit that performs dual authentication based on the UID data and the encoding data; and a command unit that commands the unlocking of the electronic locking device when the dual authentication on the UID data and the encoding data is successfully performed.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: February 18, 2020
    Inventor: Bum Soo Kim
  • Patent number: 9799154
    Abstract: The invention relates to an electronic key (32) having at least two contacts (324, 325, 326) for the transmission of data and/or energy to an electronic lock (16). In accordance with the invention, the housing (321) of the electronic key (32) comprises an input device (33) for the entry of an authorization code (36). The invention also relates to an electronic closure system with an electronic key (32) and an electronic lock (16) as well as to a method for secure acquisition of an access authorization or for secure delivery of a key to at least one user (22) by means of an electronic lock (16) and at least one electronic key (32) carried by the user (22).
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: October 24, 2017
    Assignee: Lock Your World GmbH & Co. KG
    Inventors: Manuela Engel-Dahan, Ralf Knobling, Thilo Meisel
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8999793
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8987782
    Abstract: There is provided a compound semiconductor wafer that is suitably used to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack is epitaxially grown on the second semiconductor.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Chemical Company, Limited
    Inventor: Osamu Ichikawa
  • Patent number: 8975674
    Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: March 10, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Chun-Lin Chu, Shu-Han Hsu, Guang-Li Luo, Chee-Wee Liu
  • Patent number: 8963151
    Abstract: A high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hoon Lee, Ki Se Kim
  • Patent number: 8884268
    Abstract: The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Chen, Han-Chin Chiu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 8853744
    Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Michael A. Briere
  • Patent number: 8816391
    Abstract: An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8796054
    Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventor: Alexander Usenko
  • Patent number: 8754393
    Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Aaron D. Franklin, Joshua T. Smith
  • Publication number: 20140131768
    Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: National Applied Research Laboratories
    Inventors: Chun-Lin Chu, Shu-Han Hsu, Guang-Li Luo, Chee-Wee Liu
  • Patent number: 8716695
    Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Conal E. Murray
  • Patent number: 8685841
    Abstract: The present invention is directed to a novel synthetic method for producing nanoscale heterostructures, and particularly nanoscale heterostructure particles, rods and sheets, that comprise a metal core and a monocrystalline semiconductor shell with substantial lattice mismatches between them. More specifically, the invention concerns the use of controlled soft acid-base coordination reactions between molecular complexes and colloidal nanostructures to drive the nanoscale monocrystalline growth of the semiconductor shell with a lattice structure incommensurate with that of the core. The invention also relates to more complex hybrid core-shell structures that exhibit azimuthal and radial nano-tailoring of structures. The invention is additionally directed to the use of such compositions in semiconductor devices.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 1, 2014
    Assignee: University of Maryland College Park
    Inventors: Jiatao Zhang, Yun Tang, Min Ouyang
  • Publication number: 20140084239
    Abstract: Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung, Dipanjan Basu, Sanaz K. Gardner, Satyarth Suri, Ravi Pillarisetty, Niloy Mukherjee, Han Wui Then, Robert S. Chau
  • Publication number: 20140053894
    Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Patent number: 8653616
    Abstract: It is aimed to provide a photoelectric conversion device having high adhesion between a first semiconductor layer and an electrode layer as well as high photoelectric conversion efficiency. A photoelectric conversion device comprises an electrode layer, a first semiconductor layer located on the electrode layer and comprising a chalcopyrite-based compound semiconductor of group I-III-VI and oxygen, and a second semiconductor layer located on the first semiconductor layer and forming a pn junction with the first semiconductor layer. In the photoelectric conversion device, the first semiconductor layer has a higher molar concentration of oxygen in a part located on the electrode layer side with respect to a center portion in a lamination direction of the first semiconductor layer than a molar concentration of oxygen in the whole of the first semiconductor layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 18, 2014
    Assignee: KYOCERA Corporation
    Inventors: Rui Kamada, Shuichi Kasai
  • Patent number: 8633471
    Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include a modulation doped heterostructure, wherein the modulation doped heterostructure may comprise an active portion having a first bandgap and a delta doped portion having a second bandgap.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
  • Patent number: 8633514
    Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Tatsuya Tanabe, Katsushi Akita, Hideaki Nakahata, Hiroshi Amano
  • Patent number: 8633466
    Abstract: A compound semiconductor device includes: a substrate; a first compound semiconductor layer formed over the substrate; a second compound semiconductor layer formed over the first compound semiconductor layer; and an upper electrode formed over the first compound semiconductor layer, wherein two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance from the upper electrode.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Limited
    Inventor: Naoya Okamoto
  • Publication number: 20140014967
    Abstract: The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Chen, Han-Chin Chiu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 8629478
    Abstract: A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8618556
    Abstract: An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Yao-Tsung Huang, Clement Hsingjen Wann
  • Publication number: 20130320404
    Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventor: Alexander Usenko
  • Patent number: 8558285
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Publication number: 20130256629
    Abstract: Graphene semiconductor device, a method of manufacturing a graphene semiconductor device, an organic light emitting display and a memory, include forming a multilayered member including a sacrificial substrate, a sacrificial layer, and a semiconductor layer deposited in sequence, forming a transfer substrate on the semiconductor layer, forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sacrificial substrate from the semiconductor layer, forming a second laminate by forming a graphene layer on a base substrate, combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer, and removing the transfer substrate.
    Type: Application
    Filed: June 14, 2012
    Publication date: October 3, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang Seung LEE, Young Bae KIM, Young Jun YUN, Yong Sung KIM, David SEO, Joo Ho LEE
  • Publication number: 20130256760
    Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Errol Antonio C. Sanchez, David K. Carlson, Zhiyuan Ye
  • Patent number: 8507952
    Abstract: To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 13, 2013
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Sadanori Yamanaka, Tomoyuki Takada, Masahiko Hata
  • Patent number: 8492771
    Abstract: A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: July 23, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Rüb, Michael Treu, Armin Willmeroth, Franz Hirler
  • Publication number: 20130161637
    Abstract: Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: SOITEC
    Inventors: Christiaan J. Werkhoven, Chantal Arena
  • Patent number: 8441036
    Abstract: A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: May 14, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yoshio Shimoida, Tetsuya Hayashi, Hideaki Tanaka, Shigeharu Yamagami, Masakatsu Hoshi
  • Patent number: 8426892
    Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: April 23, 2013
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Patent number: 8399314
    Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Conal E. Murray, Michael J. Rooks
  • Patent number: 8399912
    Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 19, 2013
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Michael A. Briere
  • Publication number: 20130062665
    Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 14, 2013
    Applicant: NASP III/V GMBH
    Inventor: Bernardette Kunert
  • Publication number: 20130056793
    Abstract: Embodiments of the invention provide methods for forming high quality, low resistivity Group III-V or Group II-VI compounds. In one embodiment, the method includes growing a compound semiconductor layer having a n-type or p-type dopant over a substrate, the compound semiconductor layer comprising at least a first component and a second component, and the second component has a vapor pressure relatively higher than the first component, forming a supplemental layer consisted essentially of the second component at or near an upper surface of the compound semiconductor layer, and anneal the substrate. A capping layer may be formed on the supplemental layer to help prevent loss of crystallinity of the second component at elevated temperatures. An overpressure of the second component gas may be provided onto an exposed surface of the substrate during annealing to enhance the surface morphology of the compound semiconductor layer.
    Type: Application
    Filed: August 20, 2012
    Publication date: March 7, 2013
    Applicant: Applied Materials, Inc.
    Inventor: SWAMINATHAN T. SRINIVASAN
  • Publication number: 20130032856
    Abstract: A semiconductor apparatus includes: a semiconductor apparatus includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a third semiconductor layer of the first conductivity type, wherein: the second semiconductor layer is formed between the first and third semiconductor layers, and the first and second semiconductor layers are in contact with each other; and a first energy level at a bottom edge of a conduction band of the first semiconductor layer is lower than a second energy level at a top edge of a valence band of the second semiconductor layer, and the second energy level at the top edge of the valence band of the second semiconductor layer is substantially the same as a third energy level at a bottom edge of a conduction band of the third semiconductor layer.
    Type: Application
    Filed: June 26, 2012
    Publication date: February 7, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Tsuyoshi TAKAHASHI
  • Publication number: 20130001591
    Abstract: An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Yao-Tsung Huang, Clement Hsingjen Wann
  • Publication number: 20120326212
    Abstract: A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.
    Type: Application
    Filed: September 9, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Fompeyrine, Edward W. Kiewra, Steven J. Koester, Devendra K. Sadana, David J. Webb
  • Publication number: 20120326646
    Abstract: A power semiconductor module includes an element pair formed by connecting, in anti-parallel to each other, an IGBT and an FWD group in which an FWD, a voltage drop characteristic of which during conduction has a negative temperature coefficient, and an FED, a voltage drop characteristic of which during conduction has a positive temperature coefficient, are connected in series and an element pair formed by connecting, in anti-parallel to each other, an IGBT and an FWD group in which a FWD, a voltage drop characteristic of which during conduction has a negative temperature coefficient, and an FWD, a voltage drop characteristic of which during conduction has a positive temperature coefficient, are connected in series. The element pairs are connected in parallel.
    Type: Application
    Filed: October 29, 2010
    Publication date: December 27, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Tanaka, Shinichi Kinouchi
  • Publication number: 20120326209
    Abstract: To provide a semiconductor device including a functional laminate having flatness and crystallinity improved by effectively passing on the crystallinity and flatness improved in a buffer to the functional laminate, and to provide a method of producing the semiconductor device; in the semiconductor device including the buffer and the functional laminate having a plurality of nitride semiconductor layers, the functional laminate includes a first n-type or i-type AlxGa1-xN layer (0?x<1) on the buffer side, and an AlzGa1-zN adjustment layer containing p-type impurity, which has an approximately equal Al composition to the first AlxGa1-xN layer (x?0.05?z?x+0.05, 0?z<1) is provided between the buffer and the functional laminate.
    Type: Application
    Filed: March 1, 2011
    Publication date: December 27, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
  • Publication number: 20120313106
    Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventor: Zhi He
  • Publication number: 20120307534
    Abstract: An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Atsushi YAMADA
  • Patent number: 8314023
    Abstract: Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: November 20, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Xiaoyu Yang, Roy E. Scheuerlein, Feng Li, Albert T. Meeks
  • Publication number: 20120280274
    Abstract: A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si1-xGex layer with low Ge content; and a Ge-containing layer formed on the porous structure layer, in which the Ge-containing layer comprises a Ge layer or a Si1-yGey layer with high Ge content and x?y. Further, a method for forming the semiconductor structure is also provided.
    Type: Application
    Filed: September 7, 2011
    Publication date: November 8, 2012
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Publication number: 20120280275
    Abstract: Provided is a semiconductor wafer including: a base wafer whose surface is made of a silicon crystal: a SixGe1-xC (0?x<1) epitaxial crystal formed in a partial area of the silicon crystal; and a Group 3 nitride semiconductor crystal formed on the SixGe1-xC (0?x<1) epitaxial crystal. In one example, the semiconductor wafer includes an inhibitor that is formed on the silicon crystal, contains an aperture exposing the silicon crystal, and inhibits crystal growth, and the SixGe1-xC (0?x<1) epitaxial crystal is formed in the aperture.
    Type: Application
    Filed: July 13, 2012
    Publication date: November 8, 2012
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko HATA, Hiroyuki SAZAWA
  • Publication number: 20120280233
    Abstract: A high efficiency heterostructure field effect transistor (HFET) capable of suppressing a leakage current and enhancing a current density by lowering a barrier between an electrode and a semiconductor layer is provided. The high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.
    Type: Application
    Filed: September 6, 2011
    Publication date: November 8, 2012
    Inventors: Jae Hoon LEE, Ki Se Kim
  • Publication number: 20120273839
    Abstract: A semiconductor wafer includes a base wafer, a sacrificial layer that is lattice-matched or pseudo lattice-matched to the base wafer, a first crystal layer that is formed on the sacrificial layer and made of an epitaxial crystal of SixGe1-x, (0?x<1), and a second crystal layer that is formed on the first crystal layer and made of an epitaxial crystal of a group 3-5 compound semiconductor having a larger band gap than the first crystal layer. The base wafer is, for example, made of single-crystal GaAs. The sacrificial layer is, for example, made of an epitaxial crystal of InmAlnGa1-m-nAs (0?m<1, 0<n?1, 0<n+m?1).
    Type: Application
    Filed: June 22, 2012
    Publication date: November 1, 2012
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko HATA, Hisashi YAMADA, Tomoyuki TAKADA
  • Publication number: 20120273840
    Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
    Type: Application
    Filed: April 25, 2011
    Publication date: November 1, 2012
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu