Abstract: A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.

Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Abstract: A silicon carbide substrate has a substrate surface. A gate insulating film is provided to cover a part of the substrate surface. A gate electrode covers a part of the gate insulating film. A contact electrode is provided on the substrate surfaces, adjacent to and in contact with the gate insulating film, and it contains an alloy having Al atoms. Al atoms do not diffuse from the contact electrode into a portion of the gate insulating film lying between the substrate surface and the gate electrode.

Abstract: A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm?3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.

Abstract: A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j?N2j>N1d and N2j<N2b are satisfied.

Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.

Abstract: Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [1-100], [-1010], and [01-01] of the substrate from a [0001] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.

Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

Abstract: A semiconductor device having a substrate, and at least one contact, situated on and/or above a surface of the substrate, having at least one layer made of a conductive material, the conductive material including at least one metal. The layer made of the conductive material is sputtered on, and has tear-off marks on at least one outer side area between an outer base area facing the surface and an outer contact area facing away from the surface. A manufacturing method for a semiconductor device having at least one contact is also described.

Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.

Abstract: According to the present invention, there is provided an SiC epitaxial wafer which reduces triangular defects and stacking faults, which is highly uniform in carrier concentration and film thickness, and which is free of step bunching, and its method of manufacture. The SiC epitaxial wafer of the present invention is an SiC epitaxial wafer in which an SiC epitaxial layer is formed on a 4H—SiC single crystal substrate that is tilted at an off angle of 0.4°-5°, wherein the density of triangular-shaped defects of said SiC epitaxial layer is 1 defect/cm2 or less.

Abstract: Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.

Abstract: A semiconductor power device includes a SiC semiconductor body. At least part of the SiC semiconductor body constitutes a drift zone. A first contact is at a first side of the SiC semiconductor body. A second contact is at a second side of the SiC semiconductor body. The first side is opposite the second side. A current path between the first contact and the second contact includes at least one graphene layer.

Abstract: Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using laser-assisted chemical vapor deposition (LA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to light and/or heat. The freestanding film is then exposed to a laser beam in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.

Abstract: A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first region of a second conductivity type selectively provided in a first major surface of the semiconductor layer, a second region of the second conductivity type selectively provided in the first major surface and connected to the first region, a first electrode provided in contact with the semiconductor layer and the first region, a second electrode provided in contact with the second region, and a third electrode electrically connected to a second major surface of the semiconductor layer opposite to the first major surface.

Abstract: A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a first conductivity type semiconductor layer that is formed on the substrate and is made of silicon carbide; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a first electrode provided on the active area; and a second electrode provided on the rear surface of the semiconductor substrate.

Abstract: A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.

Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

Abstract: Marking of an SiC wafer with an identifier is realized by irradiation with a pulsed laser using a harmonic of a wavelength four times that of a YAG laser. A speed at which a laser head moves, an orbit in which the laser head moves, the output power and Q-switch frequency of a pulsed laser to be applied, and the like are determined such that pulse-irradiated marks formed as a result of irradiation with corresponding pulses of the pulsed laser do not overlap each other.

Abstract: A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 ?m or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 ?m or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.

Abstract: A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region, and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer having a sheet resistance between approximately 103 Ohms per square and approximately 107 Ohms per square. During direct current and/or low frequency operation, the field-controlling element can behave similar to a metal electrode. However, during high frequency operation, the field-controlling element can behave similar to an insulator.

Abstract: A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the surface of the semiconductor layer. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer and the insulating film is not less than 1×1021 cm?3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the <?2110> direction in the surface of the semiconductor layer. A method of manufacturing the silicon carbide semiconductor device is also provided.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.

Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Abstract: The invention relates to a production method for a unipolar semiconductor component having a drift layer (16), comprising the following step: forming the drift layer (16) with a continuously decreasing concentration of a charge carrier doping (n) along the growth direction (19) of the drift layer (16) by way of epitaxial precipitation of the material of the drift layer (16), which comprises at least one wide band gap material. By using silicon carbide for the drift layer (16) formed by the epitaxial precipitation, a subsequent change of the continuously decreasing concentration of the charge carrier doping (n) due to a diffusion of the dopant atoms in downstream processes is suppressed. The production method can be used in particular to implement a unipolar semiconductor component comprising a drift layer (16), which component has an advantageous ratio of a comparatively high reverse bias voltage with relatively low forward losses, in a simple and/or cost-effective manner.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A MOSFET includes: a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an active layer; a gate oxide film; a p type body region having p type conductivity and formed to include a region of the active layer, the region being in contact with the gate oxide film; an n+ region having n type conductivity and formed in the p type body region to include a main surface of the active layer opposite to the silicon carbide substrate; and a source contact electrode formed on the active layer in contact with the n+ region, the p type body region having a p type impurity density of 5×1017 cm?3 or greater, the source contact electrode and the p type body region being in direct contact with each other.

Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.

Abstract: The present invention relates to a coating system on a substrate with improved protection against wear as well as corrosion. According to the invention the substrate is coated with a diamond like carbon (DLC) layer. This DLC layer is coated with an additional layer with material different from the DLC coating material, thereby closing the pin holes of the DLC layer.

Abstract: A first silicon carbide substrate has a first backside surface connected to a supporting portion, a first front-side surface opposite to the first backside surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. A second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface opposite to the second backside surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A closing portion closes the gap. Thereby, foreign matters can be prevented from remaining in a gap between a plurality of silicon carbide substrates provided in a combined substrate.

Abstract: A silicon carbide substrate, which achieves restrained warpage even when a different-type material layer made of a material other than silicon carbide, includes: a base layer made of silicon carbide; and a plurality of SiC layers arranged side by side on the base layer when viewed in a planar view and each made of single-crystal silicon carbide. A gap is formed between end surfaces of adjacent SiC layers.

Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

Abstract: A semiconductor device 100 includes: a silicon carbide layer 102; a source region 104 of a first conductivity type disposed in the silicon carbide layer; a body region 103 of a second conductivity type disposed at a position in contact with the source region 104 in the silicon carbide layer; a contact region 105 of the second conductivity type formed in the body region; a drift region 102d of the first conductivity type disposed in the silicon carbide layer; and a source electrode 109 in ohmic contact with the source region 104 and the contact region 105, wherein: a side wall of the source electrode 109 is in contact with the source region 104; a lower surface of the source electrode 109 is in contact with the contact region 105 and is not in contact with the source region 104; and at least a portion of the source region 104 overlaps the contact region 105 as viewed from a direction perpendicular to a principle surface of a substrate 101.

Abstract: A system for crystal growth having rapid heating and cooling. A fluid-cooling jacket having a reflective shield contained therein is disposed around a heating cylinder in which crystal growth takes place. A heating coil is disposed round the cooling jacket. The invention also includes a method of crystal growth and semiconductor devices formed using the inventive methods and systems.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.

Abstract: Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first ohmic electrode ohmic-contacting the semiconductor layer; a second ohmic electrode ohmic-contacting the semiconductor layer and spaced apart from the first ohmic electrode; and a schottky electrode unit schottky-contacting the semiconductor layer and covering the second ohmic electrode.

Abstract: Provided is a silicon carbide epitaxial wafer, the entire surface of which is free of step bunching. Also provided is a method for manufacturing said silicon carbide epitaxial wafer. The provided method for manufacturing a silicon carbide semiconductor device includes: a step wherein a 4H—SiC single-crystal substrate having an off-axis angle of 5° or less is polished until the lattice disorder layer on the surface of the substrate is 3 nm or less; a step wherein, in a hydrogen atmosphere, the polished substrate is brought to a temperature between 1400° C. and 1600° C. and the surface of the substrate is cleaned; a step wherein silicon carbide is epitaxially grown on the surface of the cleaned substrate as the amounts of SiH4 gas and C3H8 gas considered necessary for epitaxially growing silicon carbide are supplied simultaneously at a carbon-to-silicon concentration ratio between 0.7 and 1.

Abstract: A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer.

Abstract: A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.

Abstract: According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package.

Abstract: A silicon carbide semiconductor device is provided which has a lower on-resistance and a higher breakdown voltage than those of a conventional silicon carbide semiconductor device. A JFET includes an n type substrate, a p type layer, an n type layer, a source region, a drain region, and a gate region. The n type substrate has a main surface having an off angle of not less than 32° relative to the {0001} plane, and is made of silicon carbide (SiC). The p type layer is formed on the main surface of the n type substrate, and has p type conductivity. The n type layer is formed on the p type layer, and has n type conductivity. The source region and the drain region are formed in n type layer with a space interposed therebetween. The gate region is formed in the n type layer at a region between the source region and the drain region.