Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1?x?y)Si(s)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.

Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.

Abstract: The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Abstract: The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 ?m or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired.

Abstract: The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC.

Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.

Abstract: A process for producing a semiconductor-on-sapphire article, including: forming a barrier layer and a semiconductor layer on a sapphire substrate, the barrier layer being disposed between the sapphire substrate and the semiconductor layer to inhibit at least one of aluminium from the sapphire and extended defects arising from the sapphire-semiconductor interface from entering the semiconductor layer; wherein the semiconductor is at least one of silicon and a silicon-germanium alloy.

Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.

Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.

Abstract: An enhancement mode (E-mode) HEMT is provided that can be used for analog and digital applications. In a specific embodiment, the HEMT can be an AlN/GaN HEMT. The subject E-mode device can be applied to high power, high voltage, high temperature applications, including but not limited to telecommunications, switches, hybrid electric vehicles, power flow control and remote sensing. According to an embodiment of the present invention, E-mode devices can be fabricated by performing an oxygen plasma treatment with respect to the gate area of the HEMT. The oxygen plasma treatment can be, for example, an O2 plasma treatment. In addition, the threshold voltage of the E-mode HEMT can be controlled by adjusting the oxygen plasma exposure time. By using a masking layer protecting regions for depletion mode (D-mode) devices, D-mode and E-mode devices can be fabricated on a same chip.

Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a plurality of SiC substrates each made of single-crystal silicon carbide; forming a base layer made of silicon carbide and holding the plurality of SiC substrates, which are arranged side by side when viewed in a planar view; and forming a filling portion filling a gap between the plurality of SiC substrates.

Abstract: A Schottky-barrier junction element 1 has a Schottky-barrier junction between an organic semiconductor 3 and an organic conductor 4. The inorganic semiconductor 3 is any one of nitride semiconductors, Si, GaAs, CdS, CdTe, CuInGaSe, InSb, PbTe, PbS, Ge, InN, GaSb, and SiC. A solar cell uses this Schottky-barrier junction element 1, with its photoelectric conversion section including the Schottky junction. A photoelectric conversion element uses this Schottky-barrier junction element 1, with its conversion section for interconverting light and electricity including the Schottky junction.

Abstract: A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. A coating film made of Si is formed on an initial growth layer on a 4H—SiC substrate, and an extended terrace surface is formed in a region covered with the coating film. Next, the coating film is removed, and a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion made of 3C—SiC crystals having a polytype stable at a low temperature is grown on the extended terrace surface of the initial growth layer. A channel region of a MOSFET or the like is provided in the 3C—SiC portion having a narrow band gap. As a result, the channel mobility is improved because of a reduction in an interface state, and a silicon carbide semiconductor device having excellent performance characteristics is obtained.

Abstract: A silicon carbide substrate allowing reduction in cost for manufacturing a semiconductor device including a silicon carbide substrate includes a base substrate composed of silicon carbide and an SiC layer composed of single crystal silicon carbide different from the base substrate and arranged on the base substrate in contact therewith. Thus, the silicon carbide substrate 1 is a silicon carbide substrate capable of making effective use of silicon carbide single crystal.

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

Abstract: One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

Abstract: A nitride-based compound semiconductor includes an atom of at least one group-III element selected from the group consisting of Al, Ga, In, and B, a nitrogen atom, and a metal atom that forms a compound by bonding with an interstitial atom of the at least one group-III element. The metal atom is preferably iron or nickel, A doping concentration of the metal atom is preferably equal to a concentration of the interstitial atom of the at least one group-III element.

Abstract: The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type made of SiC, a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer, a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region, source regions of the first conductivity type formed on a surface layer portion of the body region adjacently to side surfaces of the gate trench, a gate insulating film formed on the bottom surface and the side surfaces of the gate trench so that the thickness of a portion on the bottom surface is greater than the thickness of portions on the side surfaces, a gate electrode embedded in the gate trench through the gate insulating film, and an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the t

Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.

Abstract: According to one embodiment, provided are a package utilized for a high frequency semiconductor device and a fabrication method for such the package, the package including: a conductive base plate including a CTE control layer composed of compound material, and a heat conduction layer disposed on the CTE control layer and composed of Cu.

Abstract: In a structure for crystalline material growth, there is provided a lower growth confinement layer and an upper growth confinement layer that is disposed above and vertically separated from the lower growth confinement layer. A lateral growth channel is provided between the upper and lower growth confinement layers, and is characterized by a height that is defined by the vertical separation between the upper and lower growth confinement layers. A growth seed is disposed at a site in the lateral growth channel for initiating crystalline material growth in the channel. A growth channel outlet is included for providing formed crystalline material from the growth channel. With this growth confinement structure, crystalline material can be grown from the growth seed to the lateral growth channel outlet.

Abstract: A semiconductor device includes a first GaN layer provided on a SIC substrate, a second GaN layer provided on the first GaN layer, and an electron supply layer that is provided on the second GaN layer and has a band gap greater than that of GaN, the first GaN layer having an acceptor concentration higher than that of the second GaN layer.

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; forming a Si film made of silicon on a main surface of the base substrate; fabricating a stacked substrate by placing the SiC substrate on and in contact with the Si film; and connecting the base substrate and the SiC substrate to each other by heating the stacked substrate to convert, into silicon carbide, at least a region making contact with the base substrate and a region making contact with the SiC substrate in the Si film.

Abstract: A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.

Abstract: A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.

Abstract: A method of cleaning an SiC semiconductor capable of exhibiting an effect of cleaning an SiC semiconductor is provided. An SiC semiconductor and an SiC semiconductor device capable of achieving improved characteristics are provided. The method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor (step S2) and removing the oxide film (step S3). In the forming step (step S2), the oxide film is formed in a dry atmosphere at a temperature not lower than 700° C. that contains O element. The SiC semiconductor is an SiC semiconductor having a surface and the surface has metal surface density not higher than 1×1012 cm?2. The SiC semiconductor device includes an SiC semiconductor and an oxide film formed on a surface of the SiC semiconductor.

Abstract: A method for producing n-type SiC single crystal, including: adding gallium and nitrogen, which is a donor element, for obtaining an n-type semiconductor during crystal growth of SiC single crystal, such that the amount of nitrogen as represented in atm unit is greater than the amount of gallium as represented in atm unit; an n-type SiC single crystal obtained according to this production method; and, a semiconductor device that includes the n-type SiC single crystal.

Abstract: A chip size package includes: a radio frequency substrate having a radio frequency semiconductor circuit formed on a principal surface; a semiconductor cover substrate arranged at a position facing the principal surface of the radio frequency substrate; and a joining frame arranged in a manner such as to surround the radio frequency semiconductor circuit between the radio frequency substrate and the semiconductor cover substrate, the joining frame joining the radio frequency substrate and the semiconductor cover substrate, wherein: the radio frequency substrate further has a wire formed on a surface opposite to the principal surface; and the radio frequency semiconductor circuit and the wire are electrically connected to each other through a via hole penetrating through the radio frequency substrate in a thickness direction thereof.

Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

Abstract: A silicon carbide substrate has a substrate region and a support portion. The substrate region has a first single crystal substrate. The support portion is joined to a first backside surface of the first single crystal. The dislocation density of the first single crystal substrate is lower than the dislocation density of the support portion. At least one of the substrate region and the support portion has voids.

Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.

Abstract: There is provided a method of manufacturing a semiconductor device, a semiconductor device, and a semiconductor apparatus, by which an electrode having an excellent ohmic property can be formed, and a semiconductor device having excellent device characteristics can be obtained with a high product yield.

Abstract: A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die.

Abstract: There is provided a silicon carbide semiconductor device equipped with an ohmic electrode that exhibits both low contact resistance and favorable surface conditions, the silicon carbide semiconductor device including a p-type silicon carbide single crystal, and an ohmic electrode for the p-type silicon carbide single crystal, wherein the ohmic electrode includes an alloy layer containing at least titanium, aluminum and silicon, and ratios of titanium, aluminum, and silicon in the alloy layer are Al: 40 to 70% by mass, Ti: 20 to 50% by mass, and Si: 1 to 15% by mass.

Abstract: A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.

Abstract: A semiconductor device includes a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined, and a plurality of spaced apart doped regions within the active region. The plurality of doped regions have a second conductivity type that is opposite the first conductivity type and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of doped regions include a plurality of rows extending in a longitudinal direction. Each of the rows includes a plurality of longitudinally extending segments, and the longitudinally extending segments in a first row at least partially overlap the longitudinally extending segments in an adjacent row in a lateral direction that is perpendicular to the longitudinal direction.

Abstract: Embodiments of a high electron mobility transistor with recessed barrier layer, and methods of forming the same, are disclosed. Other embodiments are also be described and claimed.

Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).

Abstract: A supporting portion is made of silicon carbide. At least one layer has first and second surfaces. The first surface is supported by the supporting portion. The at least one layer has first and second regions. The first region is made of silicon carbide of a single-crystal structure. The second region is made of graphite. The second surface has a surface formed by the first region. The first surface has a surface formed by the first region, and a surface formed by the second region. In this way, a semiconductor substrate can be provided which has a region made of silicon carbide having a single-crystal structure and a supporting portion made of silicon carbide and allows for reduced electric resistance of an interface therebetween.

Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than ?40 ?m and not greater than ?5 ?m, and a value for warp at the main surface being not smaller than 5 ?m and not greater than 40 ?m. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.

Abstract: A semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member is provided. An n? SiC layer, a source contact electrode formed on a main surface of the n? SiC layer, a gate electrode arranged at a distance from the source contact electrode on the main surface of the n? SiC layer, and an interlayer insulating film located between the source contact electrode and the gate electrode are provided. A rate of lowering in electric resistance in the interlayer insulating film when heating to a temperature not higher than 1200° C. is carried out while the source contact electrode and the interlayer insulating film are adjacent to each other is not higher than 5%.

Abstract: Provided is a method for manufacturing a low-cost bonded wafer (8) which allows bulk crystals of a wide bandgap semiconductor (1) to be transferred onto a handle substrate (3) as thinly as possible without breaking the substrate. More specifically, provided is a method for manufacturing a bonded wafer (8) by forming a wide bandgap semiconductor film (4) on a surface of a handle substrate (3), the method comprising a step of implanting ions from a surface (5) of a wide bandgap semiconductor substrate (1) having a bandgap of 2.8 eV or more to form an ion-implanted layer (2), a step of applying a surface activation treatment to at least one of the surface of the handle substrate (3) and the ion-implanted surface (5) of the wide bandgap semiconductor substrate (1), a step of bonding the surface (5) of the wide bandgap semiconductor substrate (1) and the surface of the handle substrate (3) to obtain bonded substrates (6), a step of applying a heat treatment to the bonded substrates (6) at a temperature of 150° C.

Abstract: There is provided a semiconductor wafer having a base wafer, an insulating layer, and a SixGe1-x crystal layer (0?x<1) in the stated order. Here, at least a partial region of the SixGe1-x crystal layer (0?x<1) has been subjected to annealing, and the semiconductor wafer comprises a compound semiconductor that has a lattice match or a pseudo lattice match with the at least partial region of the SixGe1-x crystal layer (0?x<1). Furthermore, there is provided an electronic device including a substrate, an insulating layer disposed on the substrate, a SixGe1-x crystal layer (0?x<1) disposed on the insulating layer, at least a partial region of the SixGe1-x crystal layer (0?x<1) having been subjected to annealing, a compound semiconductor that has a lattice match or a pseudo lattice match with the at least partial region of the SixGe1-x crystal layer (0?x<1), and a semiconductor device formed using the compound semiconductor.

Abstract: It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, and a conductive layer connecting the chip and the antenna. Further, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a sensor device, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the sensor device. Moreover, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a battery, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the battery.

Abstract: A base portion is made of silicon carbide and has a main surface. At least one silicon carbide layer is provided on the main surface of the base portion in a manner exposing a region of the main surface along an outer edge of the main surface. At least one protection layer is provided on this region of the main surface of the base portion along the outer edge of the main surface. Thus, a silicon carbide substrate can be polished with high in-plane uniformity.

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.

Abstract: A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.