In Different Semiconductor Regions (e.g., Heterojunctions) (epo) Patents (Class 257/E29.091)
  • Patent number: 9029867
    Abstract: A light emitting device includes a substrate, multiple n-type layers, and multiple p-type layers. The n-type layers and the p-type layers each include a group III nitride alloy. At least one of the n-type layers is a compositionally graded n-type group III nitride, and at least one of the p-type layers is a compositionally graded p-type group III nitride. A first ohmic contact for injecting current is formed on the substrate, and a second ohmic contact is formed on a surface of at least one of the p-type layers. Utilizing the disclosed structure and methods, a device capable of emitting light over a wide spectrum may be made without the use of phosphor materials.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: May 12, 2015
    Assignee: RoseStreet Labs Energy, LLC
    Inventors: Wladyslaw Walukiewicz, Iulian Gherasoiu, Lothar A. Reichertz
  • Patent number: 8962458
    Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-soo Park, Moon-sang Lee
  • Patent number: 8946723
    Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base. The epitaxial substrate includes a (111) single crystal Si substrate and a buffer layer including a plurality of first lamination units. Each of those units includes a composition modulation layer formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN being alternately laminated, and a first intermediate layer made of AlyGa1-yN (0?y<1). The relationship of x(1)?x(2)? . . . ?x(n?1)?x(n) and x(1)>x(n) is satisfied, where n represents the number of laminations of each of the first and second composition layers, and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side. The second composition layer is coherent to the first composition layer, and the first intermediate layer is coherent to the composition modulation layer.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 3, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Shigeaki Sumiya, Mikiya Ichimura, Sota Maehara, Mitsuhiro Tanaka
  • Patent number: 8941118
    Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 27, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, David F. Brown, Adam J. Williams
  • Patent number: 8895335
    Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: Jonathan J. Wierer, Jr., Andrew A. Allerman
  • Patent number: 8803231
    Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: August 12, 2014
    Assignee: Seiko Instruments, Inc.
    Inventors: Tomomitsu Risaki, Jun Osanai
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8735903
    Abstract: Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum EC1; a second semiconductor layer having a discrete hole level H0; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer; wherein the discrete hole level H0 is positioned below the conduction band minimum Ec1 for zero bias applied to the gate metal layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthias Passlack
  • Patent number: 8729603
    Abstract: A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: May 20, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Nariaki Ikeda, Seikoh Yoshida
  • Publication number: 20140124788
    Abstract: Chemical vapor deposition (CVD) systems for forming layers on a substrate are disclosed. Embodiments of the system comprise at least two processing chambers that may be linked in a cluster tool. A first processing chamber provides a chamber having a controlled environmental temperature and pressure and containing a first environment for performing CVD on a substrate, and a second environment for contacting the substrate with a plasma; a substrate transport system capable of positioning a substrate for sequential processing in each environment, and a gas control system capable of maintaining isolation. A second processing chamber provides a CVD system. Methods of forming layers on a substrate comprise forming one or more layers in each processing chamber. The systems and methods are suitable for preparing Group III-V, Group II-VI or Group IV thin film devices.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventors: Philip Kraus, Boris Borisov, Thai Cheng Chua, Sandeep Nijhawan
  • Patent number: 8686402
    Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 1, 2014
    Inventors: Niti Goel, William Tsai, Jack Kavalieros
  • Publication number: 20140061693
    Abstract: According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)?Wi)/Wi?0.008.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 6, 2014
    Inventors: Hisashi YOSHIDA, Toshiki Hikosaka, Yoshiyuki Harada, Naoharu Sugiyama, Shinya Nunoue
  • Publication number: 20140054593
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Publication number: 20140008659
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen WONG, Chen-Ju YU, Fu-Wei YAO, Jiun-Lei Jerry YU, Fu-Chih YANG, Po-Chih CHEN, Chun-Wei HSU
  • Publication number: 20140001439
    Abstract: The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1?xN/AlyGa1?yN layer pairs.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu
  • Publication number: 20130341632
    Abstract: A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: HRL LABORATORIES, LLC
    Inventor: Rongming Chu
  • Publication number: 20130334570
    Abstract: An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.
    Type: Application
    Filed: October 26, 2012
    Publication date: December 19, 2013
    Applicant: WIN SEMICONDUCTORS CORP.
    Inventors: Cheng-Kuo LIN, Szu-Ju LI, Rong-Hao SYU, Shu-Hsiao TSAI
  • Patent number: 8598594
    Abstract: In a semiconductor device including a stack structure having heterojunction units formed by alternately stacking GaN (gallium nitride) films and barrier films which are different in forbidden band width, a first electrode formed in a Schottky barrier contact with one sidewall of the stack structure, and a second electrode formed in contact with the other sidewall, an oxide film is interposed between the first electrode and the barrier films. Therefore, the reverse leakage current is prevented from flowing through defects remaining in the barrier films due to processing of the barrier films, so that a reverse leakage current of a Schottky barrier diode is reduced.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: December 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Takashi Ishigaki, Akihisa Terano, Tomonobu Tsuchiya
  • Publication number: 20130313560
    Abstract: A HEMT device has a substrate; a buffer layer disposed above the substrate; a carrier supplying layer disposed above the buffer layer; a gate element penetrating the carrier supplying layer; and a drain element disposed on the carrier supplying layer. The carrier supplying layer has a non-uniform thickness between the gate element and the drain element, the carrier supplying layer having a relatively greater thickness adjacent the drain element and a relatively thinner thickness adjacent the gate element. A non-uniform two-dimensional electron gas conduction channel is formed in the carrier supplying layer, the two-dimensional electron gas conduction channel having a non-uniform profile between the gate and drain elements.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: HRL LABORATORIES, LLC
    Inventors: Sameh G. Khalil, Karim S. Boutros
  • Publication number: 20130313561
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of a device such as a transistor. The device includes a buffer layer disposed on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N), a charge-inducing layer disposed on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N), and a gate terminal disposed in the charge-inducing layer and coupled with the barrier layer to control the channel. Other embodiments may also be described and/or claimed.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: TRIQUINT SEMICONDUCTOR, INC.
    Inventor: Chang Soo Suh
  • Patent number: 8581335
    Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Patent number: 8575471
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 5, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Patent number: 8564020
    Abstract: Systems, methods, and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further, a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore, the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: October 22, 2013
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Jing Chen, Chunhua Zhou
  • Patent number: 8563984
    Abstract: Device having reduced buffer leak on GaN substrate. In HEMT device, n-GaN (n-type GaN wafer) is used as substrate 11. Non-doped AlpGa1-pN layer with non-uniform composition p is formed on substrate 11 as buffer layer 12. On buffer layer 12, channel layer 13 of semi-insulating GaN and electron supply layer 14 of n-AlGaN are sequentially formed. In buffer layer 12, substrate connection region 121 where p=0 (GaN) is formed on lower end side, and active layer connection region 122 where value of p is also 0 (GaN) is formed on upper end side (channel layer 13 side). High Al composition region 123 where value of p is set to 1 (p=1) (AlN) is formed between substrate connection region 121 and active layer connection region 122. Resistivity of the high Al composition region 123 is highest in the buffer layer.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: October 22, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Publication number: 20130270572
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Applicant: HRL LABORATORIES, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Publication number: 20130270607
    Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka, Matthias Passlack
  • Patent number: 8558285
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Patent number: 8558280
    Abstract: A semiconductor device according to the present invention including: a substrate; a compound semiconductor layer formed on the substrate; an element forming area provided in the compound semiconductor layer; and at least one semiconductor element, which includes a first main electrode and a main second electrode, wherein the at least one semiconductor element is formed in the element forming area, wherein the compound semiconductor layer includes: a first compound growth layer, which is formed on the substrate and includes the element forming area; and a second compound growth layer formed on the substrate to surround the element forming area when viewed from a plane, wherein the second compound growth layer has a crystallinity lower than a crystallinity of the first compound growth layer.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: October 15, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Publication number: 20130240895
    Abstract: A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.
    Type: Application
    Filed: August 9, 2012
    Publication date: September 19, 2013
    Inventors: Jen-Inn CHYI, Geng-Yen Lee, Hsueh-Hsing Liu
  • Publication number: 20130234146
    Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Gerhard Prechtl
  • Publication number: 20130234152
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film.
    Type: Application
    Filed: October 19, 2012
    Publication date: September 12, 2013
    Inventor: Miki YUMOTO
  • Publication number: 20130234147
    Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8525229
    Abstract: A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0?y?1, 0?z?1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Publication number: 20130175539
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 11, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk-soon CHOI, Jong-seob KIM, Jai-kwang SHIN, Chang-yong UM, Jae-joon OH, Jong-bong HA, Ki-ha HONG, In-jun HWANG
  • Publication number: 20130168686
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Wei YAO, Chen-Ju YU, Po-Chih CHEN
  • Publication number: 20130168685
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Wei YAO, Chen-Ju YU, Fu-Chih YANG, Chun Lin TSAI
  • Publication number: 20130146889
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.
    Type: Application
    Filed: October 31, 2012
    Publication date: June 13, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Publication number: 20130140525
    Abstract: A semiconductor structure includes a silicon substrate; more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer of the group III-V compound is separated by an interlayer.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Hung-Ta LIN, Chung-Yi YU, Chia-Shiung TSAI, Ho-Yung David HWANG
  • Patent number: 8441035
    Abstract: The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: May 14, 2013
    Assignee: Panasonic Corporation
    Inventors: Masahiro Hikita, Hidetoshi Ishida, Tetsuzo Ueda
  • Publication number: 20130112986
    Abstract: The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wen Hsiung, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Fu-Chih Yang
  • Publication number: 20130111977
    Abstract: The application describes methods and apparatus for chemical sensing, e.g. gas sensing, which have high sensitivity but low power operation. A sensor is described having a flexible membrane comprising a III/N heterojunction structure configured so as to form a two dimensional electron gas within said structure. A sensing material is disposed on at least part of the flexible membrane, the sensing material being sensitive to one or more target chemicals so as to undergo a change in physical properties in the presence of said one or more target chemicals. The sensing material is coupled to said heterojunction structure such that said change in physical properties of the sensing material imparts a change in stress within the heterojunction structure which modulates the resistivity of the two dimensional electron gas.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 9, 2013
    Applicant: Stichting IMEC Nederland
    Inventor: Stichting IMEC Nederland
  • Publication number: 20130099283
    Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chun-Feng Nieh, Chung-Yi Yu, Chi-Ming Chen
  • Publication number: 20130087804
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 11, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei YAO, Chun-Wei HSU, Chen-Ju YU, Jiun-Lei Jerry YU, Fu-Chih YANG, Chih-Wen HSIUNG
  • Publication number: 20130075698
    Abstract: A semiconductor device includes a first semiconductor layer provided over a substrate; an electron transit layer contacting a top of the first semiconductor layer; and a second semiconductor layer contacting a top of the electron transit layer, wherein the electron transit layer has a dual quantum well layer having a structure where a first well layer, an intermediate barrier layer, and a second well layer are sequentially stacked, an energy of a conduction band of the intermediate barrier layer is lower than an energy of conduction band of the first semiconductor layer and the second semiconductor layer, and a ground level is generated in the first and second well layers, and a first excitation level is generated in the dual quantum well layer.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 28, 2013
    Applicants: National Institute of Information and Communications Technology, Fujitsu Limited
    Inventors: Fujitsu Limited, National Institute of Information and communicatio
  • Publication number: 20130075752
    Abstract: A semiconductor device includes: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer, wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element; and the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 28, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Junji KOTANI
  • Publication number: 20130075751
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer.
    Type: Application
    Filed: August 15, 2012
    Publication date: March 28, 2013
    Applicant: Fujitsu Limited
    Inventor: Kenji IMANISHI
  • Patent number: 8404508
    Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: March 26, 2013
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
  • Publication number: 20130069076
    Abstract: Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Masayuki IWAMI, Takuya KOKAWA
  • Publication number: 20130069074
    Abstract: According to an example embodiment, a power device includes a substrate, a nitride-containing stack on the substrate, and an electric field dispersion unit. Source, drain, and gate electrodes are on the nitride-containing stack. The nitride-containing stack includes a first region that is configured to generate a larger electric field than that of a second region of the nitride-containing stack. The electric field dispersion unit may be between the substrate and the first region of the nitride-containing stack.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 21, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-won LEE, Su-hee CHAE, Jun-youn KIM, In-jun HWANG, Hyo-ji CHOI
  • Publication number: 20130069071
    Abstract: Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.
    Type: Application
    Filed: July 19, 2012
    Publication date: March 21, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto