Including Two Or More Compounds (e.g., Alloys) (epo) Patents (Class 257/E29.096)
  • Patent number: 11810342
    Abstract: A mechanism for radiation detection is disclosed. An integrated circuit usable in detecting radiation includes a plurality of readout circuits is described. A readout circuit of the plurality of readout circuits includes an integration capacitor and an averaging capacitor. The integration capacitor is coupled with a pixel of a photodetector pixel array. The pixel has a pixel area. An available area less than the pixel area is usable for layout of the integration capacitor. The integration capacitor has a capacitor area less than the available area. The averaging capacitor has an averaging capacitance greater than the integration capacitance of the integration capacitor. In some aspects, the integrated circuit further includes at least one cascaded averaging circuit coupled with the averaging capacitor.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: November 7, 2023
    Assignee: Cyan Systems
    Inventors: John Caulfield, Jon Paul Curzan, Kenton Veeder
  • Patent number: 11436823
    Abstract: A mechanism for radiation detection is disclosed. An integrated circuit usable in detecting radiation includes a plurality of readout circuits is described. A readout circuit of the plurality of readout circuits includes an integration capacitor and an averaging capacitor. The integration capacitor is coupled with a pixel of a photodetector pixel array. The pixel has a pixel area. An available area less than the pixel area is usable for layout of the integration capacitor. The integration capacitor has a capacitor area less than the available area. The averaging capacitor has an averaging capacitance greater than the integration capacitance of the integration capacitor. In some aspects, the integrated circuit further includes at least one cascaded averaging circuit coupled with the averaging capacitor.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 6, 2022
    Assignee: Cyan Systems
    Inventors: John Caulfield, Jon Paul Curzan, Kenton Veeder
  • Patent number: 8941123
    Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Cyril Cabral, Jr., Anirban Basu, Jr.
  • Patent number: 8729544
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8129717
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: March 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20110272744
    Abstract: Described herein are semiconductor structures comprising laterally varying II-VI alloy layer formed over a surface of a substrate. Further, methods are provided for preparing laterally varying II-VI alloy layers over at least a portion of a surface of a substrate comprising contacting at least a portion of a surface of a substrate within a reaction zone with a chemical vapor under suitable reaction conditions to form a laterally varying II-VI alloy layer over the portion of the surface of the substrate, wherein the chemical vapor is generated by heating at least two II-VI binary compounds; and the reaction zone has a temperature gradient of at least 50-100° C. along an extent of the reaction zone. Also described here are devices such as lasers, light emitting diodes, detectors, or solar cells that can use such semiconductor structures.
    Type: Application
    Filed: November 6, 2009
    Publication date: November 10, 2011
    Applicant: ARIZONA BOARD OF REGENTS, a body corporate acting for and on behalf of ARIZONA STATE UNIVERSITY
    Inventors: Cun-zheng Ning, Anlian Pan
  • Patent number: 8034669
    Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel
  • Patent number: 7847297
    Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: December 7, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Jeffrey N Miller, David P Bour, Virginia M Robbins, Steven D Lester
  • Publication number: 20100102309
    Abstract: To solve the foregoing problems, provided is a ZnO-based semiconductor element having an entirely novel function distinct from hitherto, using a ZnO-based semiconductor and organic matter for an active role. An organic electrode 2 is formed on a ZnO-based semiconductor 1, and an Au film 3 is formed on the organic electrode 2. An electrode formed of a multilayer metal film including a Ti film 4 and an Au film 5 is formed on the back surface of the ZnO-based semiconductor 1 so as to be opposed to the organic electrode 2. A bonding interface between the organic electrode 2 and the ZnO-based semiconductor 1 is in a pn junction-like state. Thus, rectification occurs therebetween.
    Type: Application
    Filed: February 4, 2008
    Publication date: April 29, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Ken Nakahara, Hiroyuki Yuji, Masashi Kawasaki, Akira Ohtomo, Atsushi Tsukazaki, Tomoteru Fukumura, Masaki Nakano
  • Patent number: 7671378
    Abstract: The present invention directed to photonic devices which emit or absorb light with a short wavelength formed using molybdenum oxide grown on substrates which consist of materials selected from element semiconductors, III-V or II-IV compound semiconductors, IV compound semiconductors, organic semiconductors, metal crystal and their derivatives or glasses. New inexpensive photonic devices which emit light with a wavelength from blue to deep ultraviolet rays are realized.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: March 2, 2010
    Inventor: Takashi Katoda
  • Publication number: 20090194765
    Abstract: A method of manufacturing a MESFET using ceramic materials includes providing a substrate; providing a ceramic semiconductor material to apply onto the substrate to form a first ceramic semiconductor layer; providing a ceramic semiconductor material which is blended with ions, wherein the ceramic semiconductor material is applied onto a central part of the first ceramic semiconductor layer to form a second ceramic semiconductor layer with ions; providing another ion-mixed ceramic semiconductor material is provided to apply over both sides of the first ceramic semiconductor layer to form a third ceramic semiconductor layer having ions; and respectively plating the second and third ceramic semiconductor layers with metal layers so that the second ceramic semiconductor layer has a gate electrode and the third ceramic semiconductor layer has a source and a drain. A transistor obtained by this method can be put into broader range of applications compared to III-V group transistor.
    Type: Application
    Filed: October 29, 2008
    Publication date: August 6, 2009
    Inventors: Chau-Kuang Liau, Wen-Wei Chou
  • Patent number: 7544523
    Abstract: A method of batch fabrication using established photolithographic techniques allowing nanoparticles or nanodevices to be fabricated and mounted into a macroscopic device in a repeatable, reliable manner suitable for large-scale mass production. Nanoparticles can be grown on macroscopic “modules” which can be easily manipulated and shaped to fit standard mounts in various devices.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 9, 2009
    Assignee: FEI Company
    Inventors: Gregory Schwind, Gerald Magera, Lawrence Scipioni
  • Publication number: 20090057663
    Abstract: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.
    Type: Application
    Filed: March 19, 2008
    Publication date: March 5, 2009
    Inventors: Sun-il Kim, Jae-cheol Lee, I-hun Song, Young-soo Park, Chang-jung Kim, Jae-chul Park
  • Publication number: 20080203387
    Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.
    Type: Application
    Filed: January 4, 2008
    Publication date: August 28, 2008
    Inventors: Dong-hun Kang, Stefanovich Genrikh, I-hun Song, Young-soo Park, Chang-jung Kim
  • Publication number: 20080073658
    Abstract: A semiconductor body (2), comprising a semiconductor layer sequence with an active region (3) suitable for generating radiation. The semiconductor layer sequence comprises two contact layers (6, 7), between which the active region is arranged. The contact layers are assigned a respective connection layer (12, 13) arranged on the semiconductor body. The respective connection layer is electrically conductively connected to the assigned contact layer. The respective connection layer is arranged on that side of the assigned contact layer which is remote from the active region. The connection layers are transmissive to the radiation to be generated in the active region, and the contact layers are of the same conduction type.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 27, 2008
    Applicant: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wirth