Si Compounds (e.g., Sic) (epo) Patents (Class 257/E29.104)
  • Patent number: 9621100
    Abstract: To provide a vehicular AC electric generator provided with a highly reliable electric power conversion unit. A stator of a rotary electric machine is configured to have a plurality of sets of three-phase windings, an electric power conversion unit is configured to have a plurality of sets of three-phase bridge circuits corresponding to the plurality of sets of three-phase windings, each of the three-phase windings of the stator is connected to a DC power supply via the corresponding three-phase bridge circuits of the electric power conversion unit, the plurality of sets of three-phase bridge circuits are controlled to be at different switching timings from each other, and semiconductor switches constituting respective arms in the plurality of sets of three-phase bridge circuits are configured to be one-chip MOSFETs.
    Type: Grant
    Filed: November 22, 2012
    Date of Patent: April 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takamasa Asai
  • Patent number: 9035321
    Abstract: There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 19, 2015
    Assignee: SHOWA DENKO K.K.
    Inventors: Akihiro Matsuse, Kotaro Yano
  • Patent number: 9029979
    Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: May 12, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Yoshimoto, Ryuta Tsuchiya, Naoki Tega, Digh Hisamoto, Yasuhiro Shimamoto, Yuki Mori
  • Patent number: 9018101
    Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 28, 2015
    Assignee: Georgia Tech Research Corporation
    Inventor: Walt A. De Heer
  • Patent number: 9018635
    Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Angelo Magri', Mario Giuseppe Saggio
  • Patent number: 9012922
    Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 9006748
    Abstract: This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer 22.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Koutarou Tanaka, Masao Uchida
  • Patent number: 8994034
    Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yoshinori Tsuchiya, Takashi Shinohe
  • Patent number: 8994035
    Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 8987812
    Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Makoto Mizukami
  • Patent number: 8981211
    Abstract: An interlayer structure that, in one implementation, includes a combination of an amorphous or nano-crystalline seed-layer, and one or more metallic layers, deposited on the seed layer, with the fcc, hcp or bcc crystal structure is used to epitaxially orient a semiconductor layer on top of non-single-crystal substrates. In some implementations, this interlayer structure is used to establish epitaxial growth of multiple semiconductor layers, combinations of semiconductor and oxide layers, combinations of semiconductor and metal layers and combination of semiconductor, oxide and metal layers. This interlayer structure can also be used for epitaxial growth of p-type and n-type semiconductors in photovoltaic cells.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: March 17, 2015
    Assignee: Zetta Research and Development LLC—AQT Series
    Inventors: Erol Girt, Mariana Rodica Munteanu
  • Patent number: 8952393
    Abstract: A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration NA. A relaxation region is provided in a portion of the second surface of the first drift layer. The first drift layer and the second drift layer form a drift region in which the relaxation region is buried. The second drift layer has an impurity concentration NB, NB>NA being satisfied. A body region, a source region, and a second electrode are provided on the second drift layer.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: February 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8933465
    Abstract: A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×1017 cm?3 and not higher than 1×1022 cm?3, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Tatsuo Shimizu, Johji Nishio, Takashi Shinohe
  • Patent number: 8933464
    Abstract: An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Tatsuo Shimizu, Chiharu Ota, Takashi Shinohe
  • Patent number: 8900983
    Abstract: A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage.
    Type: Grant
    Filed: May 11, 2013
    Date of Patent: December 2, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 8901571
    Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 2, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuki Nakano, Shuhei Mitani, Mineo Miura
  • Patent number: 8901568
    Abstract: A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Misako Honaga
  • Patent number: 8884378
    Abstract: A semiconductor device and a method for forming a semiconductor device are provided. The semiconductor device includes a semiconductor body with a first semiconductor region and a second semiconductor region spaced apart from each other. A first metallization is in contact with the first semiconductor region. A second metallization is in contact with the second semiconductor region. An insulating region extends between the first semiconductor region and the second semiconductor region. A semi-insulating region having a resistivity of about 103 Ohm cm to about 1014 Ohm cm is arranged on the insulating region and forms a resistor between the first metallization and the second metallization.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Daniel Schloegl
  • Patent number: 8866159
    Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm?2.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 21, 2014
    Assignee: Cree, Inc.
    Inventors: Adrian Powell, Mark Brady, Robert Tyler Leonard
  • Patent number: 8847236
    Abstract: A semiconductor substrate includes: a silicon substrate; a monocrystalline silicon carbide film formed on a surface of the silicon substrate; and a stress relieving film formed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is formed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is formed, wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: September 30, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Yukimune Watanabe
  • Patent number: 8835933
    Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: September 16, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Takahiro Nagano, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda
  • Patent number: 8829534
    Abstract: Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masao Kikuchi
  • Patent number: 8823089
    Abstract: A semiconductor power device includes a SiC semiconductor body. At least part of the SiC semiconductor body constitutes a drift zone. A first contact is at a first side of the SiC semiconductor body. A second contact is at a second side of the SiC semiconductor body. The first side is opposite the second side. A current path between the first contact and the second contact includes at least one graphene layer.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: September 2, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Patent number: 8823016
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Yoshiyuki Harada, Maki Sugai, Shinya Nunoue
  • Patent number: 8809904
    Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 19, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Patent number: 8803160
    Abstract: A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 12, 2014
    Assignees: Siced Electronics Development GmbH & Co. KG, Norstel AB
    Inventors: Alexandre Ellison, Björn Magnusson, Asko Vehanen, Dietrich Stephani, Heinz Mitlehner, Peter Friedrichs
  • Patent number: 8803252
    Abstract: A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance Ld from the first main surface. The relaxing region has a second conductivity type and has an impurity dose amount Drx. The drift layer has an impurity concentration Nd between the first main surface and the relaxing region. Relation of Drx>Ld·Nd is satisfied. Thus, a silicon carbide semiconductor device having a high breakdown voltage is provided.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8785946
    Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm?2 to about 2000 cm?2.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: July 22, 2014
    Assignee: Cree, Inc.
    Inventors: Adrian Powell, Mark Brady, Stephan G. Mueller, Valeri F. Tsvetkov, Robert T. Leonard
  • Patent number: 8778782
    Abstract: A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 15, 2014
    Assignee: IHP GmbH—Innovations for High Performance Microelectronics
    Inventors: Gunther Lippert, Jaroslaw Dabrowski, Grzegorz Lupina, Olaf Seifarth
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Patent number: 8766277
    Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Haruka Shimizu, Natsuki Yokoyama
  • Patent number: 8748948
    Abstract: A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 10, 2014
    Assignee: DENSO CORPORATION
    Inventor: Rajesh Kumar Malhan
  • Patent number: 8728923
    Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 20, 2014
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Tetsuji Kondou, Kazuhiko Sugiura, Nobuyuki Kato
  • Patent number: 8722497
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 13, 2014
    Assignees: Nissan Motor Co., Ltd., Rohm Co., Ltd.
    Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
  • Publication number: 20140124792
    Abstract: Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: Cree, Inc.
    Inventors: Helmut Hagleitner, Fabian Radulescu, Daniel Namishia
  • Patent number: 8716718
    Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 6, 2014
    Assignees: Showa Denko K.K., National Institute of Advanced Industrial Science and Technology, Central Research Institute of Electric Power Industry
    Inventors: Kenji Momose, Michiya Odawara, Keiichi Matsuzawa, Hajime Okumura, Kazutoshi Kojima, Yuuki Ishida, Hidekazu Tsuchida, Isaho Kamata
  • Publication number: 20140103363
    Abstract: A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: CREE, INC.
    Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia, Fabian Radulescu
  • Patent number: 8686434
    Abstract: There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm?3.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Takeyoshi Masuda, Keiji Wada, Masato Tsumori
  • Patent number: 8680538
    Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: March 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Tarui, Kenichi Ohtsuka, Naruhisa Miura, Yoshinori Matsuno, Masayuki Imaizumi
  • Patent number: 8679954
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 25, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Patent number: 8673709
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Patent number: 8674438
    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Bin Yang, Man Fai Ng
  • Publication number: 20140070231
    Abstract: A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Stanislav Ivanovich Soloviev, Ahmed Elasser, Alexander Viktorovich Bolotnikov, Alexey Vert, Peter Almern Losee
  • Patent number: 8653534
    Abstract: An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 18, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 8653536
    Abstract: An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8648353
    Abstract: Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: February 11, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara
  • Patent number: 8648447
    Abstract: A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Masamu Kamaga, Kazuto Takao
  • Publication number: 20140034963
    Abstract: A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Joseph Darryl Michael, Stephen Daley Arthur, Tammy Lynn Johnson, David Alan Lilienfeld
  • Publication number: 20140027781
    Abstract: A monolithic bidirectional switching device includes a drift layer having a first conductivity type and having an upper surface, and first and second vertical metal-oxide semiconductor (MOS) structures at the upper surface of the drift layer. The drift layer provides a common drain for the first and second vertical MOS structures. The first and second vertical MOS structures are protected by respective first and second edge termination structures at the upper surface of the drift layer. A monolithic bidirectional switching device according to further embodiments includes a vertical MOS structure at the upper surface of the drift layer, and a diode at the upper surface of the drift layer. The drift layer provides a drain for the vertical MOS structure and a cathode for the diode, and the vertical MOS structure and the diode are protected by respective first and second edge termination structures.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Inventor: Sei-Hyung Ryu
  • Patent number: 8624267
    Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm?2 to about 2000 cm?2.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 7, 2014
    Assignee: Cree, Inc.
    Inventors: Adrian Powell, Mark Brady, Stephan G. Mueller, Valeri F. Tsvetkov, Robert T. Leonard