Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.

Abstract: An organic light-emitting display device includes a substrate; a gate electrode disposed on the substrate, the gate electrode including a first portion of a metal oxide layer and a metal layer; a pixel electrode disposed on the substrate and including a second portion of the metal oxide layer; a gate insulating layer covering the gate electrode; a semiconductor layer disposed on the gate insulating layer and including a channel region, and first and second regions disposed outside the channel region; a first electrode connected to the first region; a second electrode connected to the second region and the pixel electrode; an ohmic contact layer disposed between the first region and the first electrode and between the second region and the second electrode; a pixel defining layer including an opening exposing the pixel electrode; an organic light-emitting layer disposed on the pixel electrode; and an opposite electrode covering the organic light-emitting layer.

Abstract: An organic field effect transistor comprising a gate electrode 2, a gate insulating layer 3, a semiconductor layer 4, a source electrode 7, and a drain electrode 8, wherein the source electrode 7 and the drain electrode 8 are composed of conductive layers 6 and 6?, and compound layers 5 and 5? comprising an acceptor compound, respectively, wherein the compound layers 5 and 5? are each located in contact with the semiconductor layer 4, and wherein the semiconductor layer 4 contains a polymer compound having an ionization potential of 5.0 eV or more.

Abstract: A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.

Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.

Abstract: A thin film transistor array panel comprises a repair line disposed in a peripheral area of a display area and being configured to repair when at least one of a gate line and a data line are disconnected, and a detour line disposed in the peripheral area and comprising at least one resistor having higher resistance than a remaining portion of the detour line, wherein both ends of the detour line are connected to the repair line to protect the array panel.

Abstract: In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5.

Abstract: A display device according to the present invention includes: a planarization layer for insulating between a gate electrode etc. and a data wiring, a drain electrode, or the like of the transistor; and a barrier layer that is formed on an upper surface or lower surface of the planarization layer and at the same time, adapted to suppress diffusion of moisture or degassing components from the planarization layer. The display device adopts a device structure effective in reducing the plasma damage on the planarization layer by devising a positional relationship between the planarization layer and the barrier layer. Also, in combination with a novel structure as a structure for a pixel electrode, effects such as an increase in luminance can be provided as well.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.

Abstract: A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a base insulating layer on the separation layer, forming a thin-film device layer on the base insulating layer, bonding a transfer layer including the base insulating layer and the thin-film device layer to a transfer body with an adhesive, causing intralayer delamination or interfacial delamination in the separation layer, and removing the transfer layer from the substrate. The thin-film device layer includes a first wiring sublayer which is located at the bottom of the thin-film device layer and which is in contact with the base insulating layer, a dielectric sublayer which is in contact with a surface of the first wiring sublayer, a semiconductor sublayer electrically insulated from the first wiring sublayer with the dielectric sublayer, and a second wiring sublayer formed subsequently to the semiconductor sublayer.

Abstract: The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which includes: an insulating film over a substrate; a first pixel electrode embedded in the insulating film; an island-shaped single-crystal semiconductor layer over the insulating film; a gate insulating film and a gate electrode; an interlayer insulating film which covers the island-shaped single-crystal semiconductor layer and the gate electrode; a wiring which electrically connects a high-concentration impurity region and the first pixel electrode to each other; a partition which covers the interlayer insulating film, the island-shaped single-crystal semiconductor layer, and the gate electrode and has an opening in a region over the first pixel electrode; a light-emitting layer formed in a region which is over the pixel electrode and surrounded by the partition; and a second pixel electrode electrically connected to the light-emitting layer.

Abstract: In a thin film transistor (TFT) structure, formation of a spacer layer is used for isolating the NI junction from an insulating layer comprising a nitride, so as to decrease the amount of current leakage and improve the electric characteristics of TFT. In a back-channel etching (BCE) type TFT device, the spacer layer (comprising an oxide layer) is substantially formed at the sidewalls of the channel regions to isolate the insulating layer (comprising silicon nitride) from the NI junctions. In an etch-stop TFT device, the spacer layer (comprising an oxide layer) is substantially formed at the sidewalls of the etch-stop layer to isolate the insulating layer (i.e. etch-stop layer) from the NI junctions.

Abstract: The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.

Abstract: A thin-film transistor substrate in which an aluminum alloy film composing a source/drain wiring is directly connected with a transparent electrode. The thin-film transistor substrate includes a gate wiring, and source wiring and drain wiring, the gate wiring and the source and drain wiring being arranged orthogonally to each other. The single-layer aluminum alloy film composing the gate wiring and the single-layer aluminum alloy film composing the source wiring and the drain wiring are the same in composition. Furthermore, display devices can be mounted with the above thin-film transistor substrates.

Abstract: Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

Abstract: A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel thereof. The Si thin film includes a polycrystal where a plurality of narrow, rectangular crystal grains are arranged. A surface of the polycrystal is flat at grain boundaries thereof. Also, an average film thickness of the boundaries of crystals of the Si thin film ranges from 90 to 110% of an intra-grain average film thickness.

Abstract: A method of fabricating a TFT array substrate that prevents mobile ions from moving from a photoresist to channels of the TFT by the gate electrode of the TFT by performing photolithography processes for ion injection after forming gate electrode of TFT and, in addition, a method of fabricating a TFT array substrate that omits a photolithography process for forming a lower electrode of a storage capacitor by forming the lower electrode of the storage capacitor by a channel doping process for a PMOS TFT.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode, a semiconductor layer, a source electrode, a drain electrode including a comb-shaped part surrounding the source electrode and a connecting part, and a pixel electrode electrically connected to the drain electrode. The scan line and the data line are arranged intersectedly and electrically insulated from each other. At least a portion of the source electrode and the drain electrode are disposed on the semiconductor layer. At least one branch of the comb-shaped part extends outside one side of the gate electrode to form a protrusion part. The connecting part extends from the comb-shaped part beyond the other side of the gate electrode. The protrusion part and the connecting part aligned with the margin of the gate electrode have a first width and a third width respectively, wherein the first width substantially equals to the third width.

Abstract: Disclosed is a TFT substrate for a display apparatus comprising a gate wiring including a gate electrode, a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area overlapping the gate electrode and the semiconductor layer under the source electrode extends outward to an area not overlapping the gate electrode. Advantageously, the present disclosure provides a TFT substrate for a display apparatus having a high aperture ratio and causing less afterimaging, and a manufacturing method of the same.

Abstract: A liquid crystal display device includes a plurality of liquid crystal cells on a substrate, a plurality of drive lines extending along first and second directions and connected to the plurality of liquid crystal cells, a plurality of pad lines extending from each of the plurality of drive lines at a first angle from one of the first and second directions, and a plurality of pads extending at the first angle and connected to each of the plurality of pad lines for supplying external drive signals.

Abstract: Thin film transistors and organic light emitting displays using the same are provided. The thin film transistor may include a substrate, a semiconductor layer, a gate electrode, and source/drain electrodes on the substrate. The semiconductor layer is composed of a P-type semiconductor layer obtained by diffusing phosphorus into a zinc oxide semiconductor. The phosphorus is doped in the semiconductor layer to a concentration ranging from about 1×1014 to about 1×1018 cm?3.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: A four-mask process thin film transistor (TFT) array substrate and a method for fabricating the same is disclosed, which prevents a semiconductor tail from being formed. An open area is thus obtained and wavy noise is prevented from occurring.

Abstract: A thin film transistor is provided. The thin film transistor includes a frame formed on a substrate and having a plurality of grooves, line-shaped semiconductors disposed in at least one of the grooves, a first electrode overlapping with the line-shaped semiconductors, and second and third electrodes connected to ends of the line-shaped semiconductors.

Abstract: A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a portion of the active pattern where the first insulation film is formed; a second insulation film on the substrate; forming a plurality of first contact holes exposing a portion of the source and drain regions and a second contact hole exposing a portion of the data line; forming a source electrode from a transparent conductive material connected to a source region within the respective first contact hole and a data line within the second contact hole; and forming a pixel and a drain electrodes from the transparent conductive material connected to a drain region within the respective first contact hole.

Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract: A low-cost and efficient process producing improved organic electronic devices such as transistors that may be used in a variety of applications is described. The applications may include radio frequency identification (RFID) devices, displays and the like. In one embodiment, the improved process is implemented by flash annealing a substrate with an energy having wavelengths ranging from about 250 nm to about 1100 nm or higher. In this flash annealing process energy having wavelengths from about 250 nm to about 350 nm or higher is substantially prevented from irradiating the substrate.

Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

Abstract: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

Abstract: An electrochromic display is disclosed which comprises an array-side substrate (10) wherein a TFT (14) and a pixel electrode (15) connected with the TFT (14) are formed, a color filter-side substrate (50) wherein a counter electrode (53) is formed, and an electrolyte layer (80) injected between the array-side substrate (10) and the color filter-side substrate (50). In this electrochromic display, the TFT (14) is formed to have an area not less than 30% of the area of the pixel, thereby supplying a larger current. Consequently, oxidation-reduction reaction in the electrochromic phenomenon proceeds at a higher rate, thereby enabling a high-speed response.

Abstract: A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source and a drain, an overcoat dielectric layer, and a transparent pixel electrode sequentially disposed on a substrate is provided. The source and the drain respectively cover portions of the channel area. The reflective pixel electrode connects the drain and covers the bumps to form an uneven surface. The overcoat dielectric layer disposed on a transistor constituted by the gate, the gate dielectric layer, the patterned semiconductor layer, the source and the drain has a contact opening exposing a portion of the reflective pixel electrode. The transparent pixel electrode is electrically connected to the reflective pixel electrode through the contact opening.

Abstract: A photosensor includes a semiconductor thin film for photoelectric conversion having a first side portion and a second side portion. A source electrode extends in the longitudinal direction of the semiconductor thin film and has a side edge portion that overlaps the first side portion of the semiconductor thin film, and a drain electrode extends in the longitudinal direction and has a side edge portion that overlaps the second side portion of the semiconductor thin film. At least one of the side edge portions of the source and drain electrodes has protruding portions which are arranged along the longitudinal direction and which overlap the semiconductor thin film, and notched portions formed between the protruding portions. An ohmic contact layer is formed between the semiconductor thin film and the protruding portions of the at least one of the side edge portions of the source and drain electrodes.

Abstract: An organic light-emitting display device includes a substrate; a gate electrode disposed on the substrate, the gate electrode including a first portion of a metal oxide layer and a metal layer; a pixel electrode disposed on the substrate so as to be insulated from the gate electrode, the pixel electrode including a second portion of the metal oxide layer; a gate insulating layer disposed on the substrate to cover the gate electrode; a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including a channel region corresponding to the gate electrode, and first and second regions disposed outside the channel region; a first electrode connected to the first region of the semiconductor layer; a second electrode connected to the second region of the semiconductor layer and the pixel electrode; an ohmic contact layer disposed between the first region of the semiconductor layer and the first electrode and between the second region of the semiconductor layer and the second electrode; a p

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line over the substrate, a data line crossing the gate line to define a pixel region and including a transparent conductive layer and an opaque conductive layer, a data pad at one end of the data line and including a transparent conductive layer, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, the pixel electrode including a transparent conductive layer.

Abstract: A transistor includes a control electrode, a first current electrode and a second current electrode. The control electrode includes a body portion, and first and second hand portions protruded from first and second ends of the body portion, respectively. The first current electrode is electrically insulated from the control electrode and disposed over a region between the first and second hand portions of the control electrode. A portion of the first current electrode is overlapped with a portion of the control electrode. The second current electrode is electrically insulated from the control electrode and partially overlapped with the body portion, the first hand portion and the second hand portion of the control electrode. Therefore, parasitic capacitance is reduced.

Abstract: One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-germanium, zinc-lead, cadmium-germanium, cadmium-tin, cadmium-lead.

Abstract: The present invention provides a display device which can obviate the occurrence of a leak current in a thin film transistor. In a display device including a substrate, and gate signal lines, an insulation film, semiconductor layers and conductor layers which are sequentially stacked on the substrate, the conductor layer forms at least a drain electrode which is connected to a drain signal line and a source electrode which is connected to a pixel electrode, and the semiconductor layer is formed in a pattern in which the semiconductor layer has a protruding portion which protrudes outwardly from the conductor layer at a portion thereof except for a distal end of the drain electrode as viewed in a plan view.

Abstract: A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

Abstract: The present invention provides a liquid crystal display device to be operated at high speed and with high precision by improving performance of a thin-film transistor without increasing cross capacity of gate lines and data lines. On an upper layer of a gate insulator GI at an intersection of gate lines GL and data lines DL to be prepared on an active matrix substrate SUB1, which makes up a liquid crystal display panel of a liquid crystal display device, an insulating material with low dielectric constant is dropped by ink jet coating method to prepare another insulator LDP in order to improve performance characteristics of the thin-film transistor to be prepared on a silicon semiconductor layer SI without increasing cross capacity on said intersection.

Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.

Abstract: An array substrate includes a gate line, a data line, a switching device, a transmissive electrode, a reflective electrode and a compensating wiring. A pixel region includes first and second regions. The switching device is connected to the gate line and the data line. The transmissive electrode is connected to the switching device. The transmissive electrode is formed in the first region. The reflective electrode is insulated from the transmissive electrode. The reflective electrode is formed in the second region that is adjacent to the first region. The compensating wiring is connected to the switching device. The compensating wiring faces the reflective electrode in the second region with an insulation layer interposed therebetween. Thus, both of a reflectivity of the reflective electrode and a transmissivity of the transmissive electrode are enhanced simultaneously, while the liquid crystal display apparatus maintains a uniform cell gap.

Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer, dry-etching the third metal layer by using the first photoresist pattern, simultaneously dry-etching the second and first metal layers by using the first photoresist pattern, dry-etching the active layer by using the first photoresist pattern, etching the first photoresist pattern to form a second photoresist pattern by which the channel region is removed and forming a source electrode and a drain electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.

Abstract: A liquid crystal display array substrate. A trench is in a substrate. A gate, a gate dielectric layer, a semiconductor layer and a doped semiconductor layer are disposed in the trench, wherein the semiconductor layer comprises a channel. A source electrode and a drain electrode are respectively electrically connected to portions of the semiconductor layer on opposite sides of the channel.

Abstract: A four-mask process thin film transistor (TFT) array substrate and a method for fabricating the same is disclosed, which prevents a semiconductor tail from being formed. An open area is thus obtained and wavy noise is prevented from occurring.

Abstract: A transistor array panel includes switching elements provided in intersecting portions between gate and data lines, and display electrodes connected to the switching elements. A conductive film pattern is provided to be electrically insulated from the gate and data lines, and display electrodes, and to be overlapped on the display electrodes, thereby forming a storage capacitance between each of the display electrodes and the conductive film pattern. A protection circuit is electrically connected to the gate and data lines, and disposed in an outer peripheral portion of a display region in which the switching elements and the display electrodes are formed on the one side of the substrate. A common line is insulated from the protection circuit, connected to the conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region.

Abstract: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.