Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
Abstract: A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.
August 5, 2011
February 7, 2013
INFINEON TECHNOLOGIES AG
Stefan Macheiner, Andreas Peter Meiser, Steffen Thiele
Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
January 31, 2011
August 2, 2012
Madhur Bobde, Harsh Naik, Lingpeng Guan, Anup Bhalla, Sik Lui
Abstract: A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolar junction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.
Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a substrate includes an n-well and a p-well adjacent the n-well. An n-type active area and a p-type active area are disposed in the n-well. The p-type active area, the n-well, and the p-well are configured to operate as an emitter, a base, and a collector of an PNP bipolar transistor, respectively, and the p-type active area surrounds at least a portion of the n-type active area so as to aid in recombining carriers injected into the n-well from the p-well before the carriers reach the n-type active area. The n-well and the p-well are configured to operate as a breakdown diode, and a punch-through breakdown voltage between the n-well and the p-well is lower than or equal to about a breakdown voltage between the p-type active area and the n-well.
Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.
Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
Abstract: An electrostatic discharge protection structure includes a first vertical bipolar junction transistor; a second vertical bipolar junction transistor, wherein the second vertical bipolar junction transistor has a common collector with the first vertical bipolar junction transistor, and the common collector has a first conductivity; a horizontal bipolar junction transistor wherein the collector of the horizontal bipolar junction transistor has a second conductivity that is a different conductivity than the first conductivity, and the base of the horizontal bipolar junction transistor is electrically coupled to the common collector of the first vertical bipolar junction transistor and the second vertical bipolar junction transistor; a first avalanche diode electrically coupled to the base and the collector of the first vertical bipolar junction transistor; and a second avalanche diode electrically coupled to the base and the collector of the second vertical bipolar junction transistor.
May 29, 2009
December 2, 2010
Vadim A. Kushner, Amaury Gendron, Chai Ean E. Gill
Abstract: An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure.
Abstract: A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolarjunction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.
Abstract: A bipolar transistor structure with multiple electrodes configured to include an enhanced base capacitive element. Alternatively, a transistor with an integrated light emitting capacitive (LEC) element at the source or drain of the transistor. The transistor may be a stand alone transistor for usage in discrete applications, or may be implemented in a pixel circuit used in a display apparatus. In the pixel circuit embodiment, driver circuitry causes appropriate charging and discharging of the LEC elements of respective pixels to provide a desired display. In one alternative, a transistor may be configured to have multiple LEC elements integrated therewith, to provide respective different colors used in forming a display.
April 30, 2009
November 4, 2010
Sony Corporation, SONY ELECTRONICS INC.
Abstract: In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to be protected and the line, and extracts, from a connection point, a current corresponding to a current flowing in the first transistor. The first and the second transistors are NPN bipolar transistors having a base and an emitter are commonly connected. A resistor is connected between the base and the emitter of the first transistor, and a diode is connected between the base and a collector.
Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.
Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.