Transistor-type Device (i.e., Able To Continuously Respond To Applied Control Signal) Patents (Class 257/E29.173)

  • Patent number: 8822978
    Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 2, 2014
    Assignee: The State of Oregon Acting by and through...
    Inventors: E. William Cowell, III, John F. Wager, Brady J. Gibbons, Douglas A. Keszler
  • Patent number: 8679969
    Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 25, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Miguel Urteaga, Richard L. Pierson, Jr., Keisuke Shinohara
  • Publication number: 20130256756
    Abstract: An integrated circuit is provided. The integrated circuit may include, but is not limited to, a plurality of heterojunction bipolar transistors, wherein each heterojunction bipolar transistor is staggered with respect to any adjacent heterojunction bipolar transistor. The plurality of heterojunction bipolar transistors may be arranged in a column, wherein each heterojunction bipolar transistor is staggered in the column with respect to any adjacent heterojunction bipolar transistor in the column in a first direction and a second direction, wherein the second direction is substantially orthogonal to the first direction.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Yun Wei
  • Publication number: 20130032927
    Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Inventors: Miguel Urteaga, Richard L. Pierson, JR., Keisuke Shinohara
  • Publication number: 20120187538
    Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 26, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20120119331
    Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
  • Publication number: 20120018738
    Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: CREE, INC.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Patent number: 8093591
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Publication number: 20110215418
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region.
    Type: Application
    Filed: February 17, 2011
    Publication date: September 8, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Wataru SAITO, Syotaro Ono, Munehisa Yabuzaki, Shunji Taniuchi, Miho Watanabe
  • Publication number: 20110215452
    Abstract: A semiconductor package includes a semiconductor device and a substrate over which the semiconductor device is mounted, wherein the substrate includes: an internal ground electrode, formed in the one side of the substrate, which is connected to the semiconductor device; two external ground electrodes, located at the opposite side of the substrate opposite to the one side of the substrate, which are electrically connected to the internal ground electrode; at least one sub-ground electrode, located between the two external ground electrodes, when seen in a plan view, and located at the opposite side of the substrate, which is electrically connected to the internal ground electrode; an internal input electrode, formed in the one side of the substrate, which is connected to the semiconductor device; and an internal output electrode, formed in the one of the substrate, which is connected to the semiconductor device.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 8, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoki SAKURA
  • Publication number: 20110169050
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Publication number: 20110101500
    Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: Analog Devices, Inc.
    Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
  • Publication number: 20110012180
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 20, 2011
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Publication number: 20100289005
    Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 18, 2010
    Inventors: E. William Cowell, III, John F. Wager, Brady J. Gibbons, Douglas A. Keszler
  • Publication number: 20100164052
    Abstract: An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: STEFAN W. WIKTOR, VLADIMIR A. MURATOV, ANTHONY L. COYLE, BERNHARD P. LANGE
  • Patent number: 7745856
    Abstract: A sensor apparatus comprising a nanotube or nanowire, a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. Also a biosensor apparatus comprising a gate electrode; a source electrode; a drain electrode; a nanotube or nanowire operatively connected to the gate electrode, the source electrode, and the drain electrode; a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: June 29, 2010
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Aleksandr Noy, Olgica Bakajin, Sonia Létant, Michael Stadermann, Alexander B. Artyukhin
  • Publication number: 20100090310
    Abstract: A bipolar transistor includes an isolation layer formed in a bipolar region on a semiconductor substrate, a conductive film formed over an upper portion of the isolation layer, n+ and p+ junction regions formed within the conductive film, a first silicide film formed over portions of an upper boundary of the n+ and p+ junction regions, the first silicide film defining openings over the upper boundary of the n+ and p+ junction regions, a second silicide film formed in the openings defined by the first silicide film over the upper boundary portions of the n+ and p+ junction regions, a plurality of plugs connected to the second silicide film, and a plurality of electrodes connected to each of the plugs.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 15, 2010
    Inventor: DO-HUN KIM
  • Publication number: 20100078724
    Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: SONY CORPORATION
    Inventors: Tsutomu Imoto, Kouzou Mawatari
  • Publication number: 20100078673
    Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 1, 2010
    Applicant: STMicroelectronics S.A.
    Inventor: Jean-Luc Morand
  • Publication number: 20100072517
    Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 25, 2010
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Peter J. Zampardi, Mike Sun
  • Patent number: 7667294
    Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: February 23, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Tatsuhiko Ikeda
  • Publication number: 20100013026
    Abstract: The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Applicant: International Business Machines Corporation
    Inventors: Roger Allen Booth, JR., Kangguo Cheng, Terence B. Hook
  • Publication number: 20090321880
    Abstract: A semicoductor device includes: a collector layer made of a first conductivity type semiconductor; an intrinsic base layer formed on the collector layer and including a second conductivity type monocrystalline silicon germanium layer; a base extraction electrode formed around the intrinsic base layer and including a second conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon germanium layer; and a first conductivity type emitter layer formed in an upper portion of the intrinsic base layer. A silicon layer is formed in the upper portion of the intrinsic base layer and the emitter layer includes an upper emitter region formed in an upper portion of the silicon layer and a lower emitter region formed below and in contact with the upper emitter region.
    Type: Application
    Filed: February 24, 2009
    Publication date: December 31, 2009
    Inventor: Shigetaka Aoki
  • Publication number: 20090256181
    Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.
    Type: Application
    Filed: March 19, 2009
    Publication date: October 15, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20090160025
    Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 25, 2009
    Applicant: Renesas Technology Corp.
    Inventor: TATSUHIKO IKEDA
  • Publication number: 20090160016
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Application
    Filed: February 18, 2009
    Publication date: June 25, 2009
    Inventors: Mitsuru ARAI, Shinichiro Wada, Hideaki Nonami
  • Publication number: 20090146258
    Abstract: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 11, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Shaoqiang ZHANG, Purakh Raj VERMA, Sanford CHU
  • Patent number: 7544978
    Abstract: A sensor apparatus comprising a nanotube or nanowire, a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. Also a biosensor apparatus comprising a gate electrode; a source electrode; a drain electrode; a nanotube or nanowire operatively connected to the gate electrode, the source electrode, and the drain electrode; a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: June 9, 2009
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Aleksandr Noy, Olgica Bakajin, Sonia Létant, Michael Stadermann, Alexander B. Artyukhin
  • Publication number: 20080246117
    Abstract: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 9, 2008
    Applicant: Texas Instruments Inccorporated
    Inventors: Sameer Pendharkar, Binghua Hu, Xinfen Celia Chen
  • Publication number: 20080211060
    Abstract: An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 4, 2008
    Inventors: Kuang-Yeh Chang, Shing-Ren Sheu, Chung-Jen Ho
  • Publication number: 20080081406
    Abstract: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.
    Type: Application
    Filed: May 18, 2007
    Publication date: April 3, 2008
    Inventors: Jae-ouk Choo, II-young Yoon, Seo-woo Nam, Ja-eung Koo
  • Publication number: 20080042242
    Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.
    Type: Application
    Filed: October 26, 2007
    Publication date: February 21, 2008
    Inventors: Jefferson Hall, Mohammed Quddus
  • Publication number: 20080017932
    Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.
    Type: Application
    Filed: October 3, 2007
    Publication date: January 24, 2008
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
  • Publication number: 20080012044
    Abstract: A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structureare n-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.
    Type: Application
    Filed: March 26, 2007
    Publication date: January 17, 2008
    Inventors: Javier SALCEDO, Juin Liou, Joseph Bernier, Donald Whitney
  • Publication number: 20070278514
    Abstract: The invention relates to a semiconductor component comprising a buried temporarily n-doped area (9), which is effective only in the event of turn-off from the conducting to the blocking state of the semiconductor component and prevents chopping of the tail current in order thus to improve the turn-off softness. Said temporarily effective area is created by implantation of K centers (10).
    Type: Application
    Filed: January 24, 2005
    Publication date: December 6, 2007
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Josef Lutz
  • Patent number: 7081662
    Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: July 25, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hsing Lee, Yu-Chang Jong