Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

Abstract: Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: Methods and apparatus for increasing the coupling coefficient of a floating gate memory device includes an MOS capacitors with self-aligning gate structures that provide increased capacitance per unit area over conventional MOS capacitors.

Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.

Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract: The invention relates to FETs with stripe cells (6). Some of the cells have alternating low and high threshold regions (10, 8) along their length. In a linear operations regime, the low threshold regions conduct preferentially and increase the current density, thereby reducing the risk of thermal runaway. By distributing the low threshold regions (10) along the length of the cells (6), the risk of current crowding is reduced.

Abstract: A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout.

Abstract: A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout.

Abstract: A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body.

Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).

Abstract: An integrated circuit system includes a first device in a first power domain, and a second device coupled to the first device in a second power domain. A circuit module is coupled between the first device and a power supply voltage or between the first device and a complementary power supply voltage in the first power domain for increasing an impedance against an ESD current flowing from the first device to the second device during an ESD event.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: An anti-fuse includes a gate dielectric layer formed over a substrate, a gate electrode including a body portion and a plurality of protruding portions extending from the body portion, wherein the body portion and the protruding portions are formed to contact on the gate dielectric layer, and a junction region formed in a portion of the substrate exposed by sidewalls of the protruding portions.

Abstract: The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2).

Abstract: Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate electrodes. By setting a gate length to be smaller than a depth of channel regions, pn junction interfaces formed of adjacent side faces of the n type impurity regions and the channel regions can be substantially vertical to a top surface of a base. With this configuration, even when reduction in size is achieved in a super junction structure, a distance between the channel regions (i.e. a current path below the gate electrode) is not reduced unnecessarily. Accordingly, an increase in resistance can be prevented. In addition, depletion layers uniformly expand in the n type semiconductor regions, and impurity concentration of the regions can be increased consequently. Accordingly, reduction in resistance can be achieved.

Abstract: The invention is directed to a method for manufacturing a high voltage device. The method includes steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in the substrate. The second doped regions are located adjacent to both sides of the first doped region respectively, and the first doped region is separated from the second doped regions with an isolation region. A gate structure is formed on the substrate between the second doped regions and a source/drain region having the second doped region is formed in the substrate adjacent to both sides of the gate structure.

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.

Abstract: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.

Abstract: A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage.

Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift region. A source region of the second conductivity is in the body region. A gate extends over a surface portion of the body region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor. A drain region of the second conductivity type is in the drift region. The drain region is laterally spaced from the body region. A first buried layer of the second conductivity type is between the substrate and drift region. The first buried layer laterally extends from under the body region to under the drain region. A second buried layer of the first conductivity type is between the first buried layer and the drift region.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

Abstract: The semiconductor regions for source and drain of unused p-channel type MISFETQp and the power supply wiring 2VDD are electrically connected and the semiconductor regions for source and drain of n-channel type MISFETQn and the power supply wiring 2VSS are electrically connected. Moreover, the switch elements 3SW1, 3SW2 are formed of the p-channel type MISFETQp and n-channel type MISFETQn in the basic cells and these switch elements 3SW1, 3SW2 are discretely arranged in the n-well NWL and p-well PWL. Thereby, noise generated in the wells can be reduced in the semiconductor device where the switch elements are provided between the power supply wiring and wells and the threshold voltage of transistor formed in the well can be controlled through the ON/OFF controls of such switch elements.

Abstract: Dielectric layers containing a chemical vapor deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Forming a layer of hafnium oxide by chemical vapor deposition and forming a layer of a lanthanide oxide by electron beam evaporation, where the layer of hafnium oxide is adjacent and in contact with the layer of lanthanide, provides a dielectric layer with a relatively high dielectric constant as compared with silicon dioxide. Forming the layer of hafnium oxide by chemical vapor deposition using precursors that do not contain carbon permits the formation of the dielectric layer without carbon contamination. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

Abstract: There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions are formed in one P-type semiconductor substrate. The N-type deep well regions are electrically isolated by the P-type semiconductor substrate. Over the N-type deep well regions, a P-type deep well region and a P-type shallow well region are formed to fabricate an N-type substrate variable-bias transistor. Over the N-type deep well region, an N-type shallow well region is formed to fabricate a P-type substrate variable-bias transistor. Further a P-type DTMOS and an N-type DTMOD are fabricated.