Field-effect Transistor (epo) Patents (Class 257/E29.242)

  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9035318
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • Patent number: 9018684
    Abstract: Methods for fabricating silicon nanowire chemical sensing devices, devices thus obtained, and methods for utilizing devices for sensing and measuring chemical concentration of selected species in a fluid are described. Devices may comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) structure.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: April 28, 2015
    Assignee: California Institute of Technology
    Inventors: Andrew P. Homyk, Michael D. Henry, Axel Scherer, Sameer Walavalkar
  • Patent number: 9013003
    Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jui Liang, Po-Chao Tsao
  • Patent number: 9006044
    Abstract: A method of manufacturing a graphene device may include forming a device portion including a graphene layer on the first substrate; attaching a second substrate on the device portion of the first substrate; and removing the first substrate. The removing of the first substrate may include etching a sacrificial layer between the first substrate and the graphene layer. After removing the first substrate, a third substrate may be attached on the device portion. After attaching the third substrate, the second substrate may be removed.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-seung Lee, Joo-ho Lee, Yong-sung Kim, Chang-youl Moon
  • Patent number: 9000485
    Abstract: An electrode structure, a GaN-based semiconductor device including the electrode structure, and methods of manufacturing the same, may include a GaN-based semiconductor layer and an electrode structure on the GaN-based semiconductor layer. The electrode structure may include an electrode element including a conductive material and a diffusion layer between the electrode element and the GaN-based semiconductor layer. The diffusion layer may include a material which is an n-type dopant with respect to the GaN-based semiconductor layer, and the diffusion layer may contact the GaN-based semiconductor layer. A region of the GaN-based semiconductor layer contacting the diffusion layer may be doped with the n-type dopant. The material of the diffusion layer may comprise a Group 4 element.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-yub Lee, Wenxu Xianyu, Chang-youl Moon, Yong-young Park, Woo-young Yang, In-jun Hwang
  • Patent number: 8994103
    Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Lin Chen, Tseng-Hsun Liu, Kuan-Yu Chen, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang
  • Patent number: 8981485
    Abstract: A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 17, 2015
    Assignee: Super Group Semiconductor Co., Ltd.
    Inventors: Hsiu-Wen Hsu, Chun-Ying Yeh, Yuan-Ming Lee
  • Patent number: 8957425
    Abstract: A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8952455
    Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8952356
    Abstract: An example embodiment relates to a semiconductor device including a semiconductor element. The semiconductor element may include a plurality of unit layers spaced apart from each other in a vertical direction. Each unit layer may include a patterned graphene layer. The patterned graphene layer may be a layer patterned in a nanoscale. The patterned graphene layer may have a nanomesh or nanoribbon structure. The semiconductor device may be a transistor or a diode. An example embodiment relates to a method of making a semiconductor device including a semiconductor element.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kook Kim, Woong Choi, Yong-wan Jin
  • Patent number: 8946721
    Abstract: A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: William K. Henson
  • Patent number: 8946824
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8933512
    Abstract: The present application discloses a MOSFET and a method for manufacturing the same.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: January 13, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Science
    Inventors: Huilong Zhu, Miao Xu, Qingqing Liang
  • Patent number: 8921868
    Abstract: A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 30, 2014
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8921946
    Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Patent number: 8900958
    Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Meng-Yueh Liu
  • Patent number: 8890209
    Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 18, 2014
    Assignee: Tsinghua University
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Patent number: 8860130
    Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 14, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 8853741
    Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Titash Rakshit, Sivakumar Mudanai
  • Patent number: 8853796
    Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: October 7, 2014
    Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.
    Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
  • Patent number: 8847333
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuang-Yuan Hsu, Jeff J. Xu
  • Patent number: 8841193
    Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
  • Patent number: 8841190
    Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 23, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Changliang Qin, Huaxiang Yin
  • Patent number: 8835982
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Patent number: 8835298
    Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni?/Pt layer at a temperature of 130° C.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Sivakumar Kumarasamy, Clemens Fitz, Markus Lenski, Jochen Poth, Kristin Schupke
  • Patent number: 8835899
    Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-jun Yang, Sun-ae Seo, Sung-hoon Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 8836033
    Abstract: Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 16, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Silai Krishnaswamy, Joseph Payne, Jeffrey Hartman
  • Patent number: 8823063
    Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Tetsuya Kakehata, Yoichi Iikubo
  • Patent number: 8816410
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 8809853
    Abstract: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Kiyoshi Kato, Atsuo Isobe
  • Patent number: 8803130
    Abstract: Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Damon B. Farmer, Yu-Ming Lin, Yu Zhu
  • Patent number: 8790961
    Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hideomi Suzawa
  • Patent number: 8785974
    Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: July 22, 2014
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao
  • Patent number: 8785989
    Abstract: The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Lucien J. Bissey, William A. Stanton
  • Patent number: 8785995
    Abstract: Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”). The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Catherine A. Dubourdieu, David J. Frank, Martin M. Frank, Vijay Narayanan, Paul M. Solomon, Thomas N. Theis
  • Patent number: 8778772
    Abstract: Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chung Foong Tan, Maciej Wiatr, Peter Javorka, Falong Zhou
  • Patent number: 8779514
    Abstract: The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 15, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qingqing Liang, Huicai Zhong, Huilong Zhu
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8772148
    Abstract: A method is provided for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xinpeng Wang, Qiyang He
  • Patent number: 8765540
    Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 1, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8754393
    Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8748987
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8735903
    Abstract: Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum EC1; a second semiconductor layer having a discrete hole level H0; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer; wherein the discrete hole level H0 is positioned below the conduction band minimum Ec1 for zero bias applied to the gate metal layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthias Passlack
  • Patent number: 8735999
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a gate electrode provided on the substrate via a gate insulator. The device further includes a source region of a first conductivity type and a drain region of a second conductivity type provided in the substrate to sandwich the gate electrode, and a channel region provided between the source and drain regions in the substrate. The gate insulator includes a first insulator portion having a first edge which is positioned on the source region and is parallel to a channel-width direction, and a second edge which is positioned on the channel or source region and is parallel to the channel-width direction, and having a first thickness. The gate insulator further includes a second insulator portion positioned on a drain region side with respect to the first insulator portion, and having a second thickness greater than the first thickness.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya Ohguro
  • Patent number: 8723236
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 8716752
    Abstract: A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 6, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove
  • Patent number: 8710538
    Abstract: A light-emitting device having at least one spacer located at a bottom surface is disclosed. In two other embodiments, an electronic display system and an electronic system having such light-emitting device are disclosed. The light-emitting device comprises a plurality of leads, a light source die, and a body. The body encapsulates a portion of the plurality of leads and the light source die. The body has a least one side surface and a bottom surface. The at least one spacer is located at the bottom surface. In use, the light-emitting device is attached to a top surface of a substrate. The spacer is configured to create an air vent between the bottom surface and the top surface of the substrate when the light-emitting device is attached to, and the spacer is in contact with the substrate.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: April 29, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Yi Feng Hwang, Yin Har Cheow
  • Patent number: 8710596
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Wen Hung
  • Patent number: 8703569
    Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Sergey Pidin