Gate Comprising Ferroelectric Layer (epo) Patents (Class 257/E29.272)
  • Patent number: 8860104
    Abstract: According to one embodiment, a semiconductor device includes, a semiconductor substrate including a plurality of fins formed in an upper surface of the semiconductor substrate in a first region to extend in a first direction, a first gate electrode extending in a second direction intersecting the first direction to straddle the fins, a first gate insulating film provided between the first gate electrode and the fins, a second gate electrode provided on the semiconductor substrate in the second region; and a second gate insulating film provided between the semiconductor substrate and the second gate electrode. A layer structure of the first gate electrode is different from a layer structure of the second gate electrode.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8729614
    Abstract: The present disclosure relates to a flexible nonvolatile ferroelectric memory device, a 1T-1R (1Transistor-1Resistor) flexible ferroelectric memory device, and a manufacturing method for the same.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: May 20, 2014
    Assignee: Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Jong-Hyun Ahn, Jonghyun Rho
  • Patent number: 8653510
    Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 18, 2014
    Assignee: SRI International
    Inventors: John Hodges, Jr., Marc Rippen, Carl Biver, Jr.
  • Patent number: 8563979
    Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate. Spacers are provided between the first and second substrates. A seal material is formed outside the matrix circuits and the peripheral driver circuits in the first and second substrates. A protective film is formed on the peripheral driver circuit has substantially a thickness equivalent to an interval between the substrates which is formed by the spacers.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Yasuyuki Arai
  • Patent number: 8455935
    Abstract: A ferroelectric film comprising polyaminodifluoroborane (PADFB). Also a memory device utilizing the ferroelectric film, a method of fabricating a ferroelectric polymer and a ferroelectric solution.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 4, 2013
    Assignees: Sony Corporation, Agency for Science, Technology, and Research
    Inventors: Takehisa Ishida, Sunil Madhukar Bhangale, Han Hong, Christina Li Lin Chai
  • Patent number: 8405166
    Abstract: The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RExAl2-xO3 with 0<x<2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: March 26, 2013
    Assignee: IMEC
    Inventors: Christoph Adelmann, Johan Swerts, Sven Van Elshocht, Jorge Kittl
  • Patent number: 8399941
    Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: March 19, 2013
    Assignee: Grandis, Inc.
    Inventors: Dmytro Apalkov, Mohamad Towfik Krounbi
  • Publication number: 20120056253
    Abstract: A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a select transistor, a lower electrode, a magnetic tunnel junction element, a first protection film, an upper electrode, and a second protection film. The select transistor is formed on the semiconductor substrate. The lower electrode is electrically connected to one diffusion layer of the select transistor. The magnetic tunnel junction element is provided on the lower electrode. The first protection film is provided on a side surface of the magnetic tunnel junction element. The upper electrode is provided on the magnetic tunnel junction element and the first protection film. The second protection film is provided on side surfaces of the upper electrode, the first protection film, and the lower electrode.
    Type: Application
    Filed: November 10, 2010
    Publication date: March 8, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayoshi IWAYAMA, Hiroyuki Kanaya
  • Publication number: 20110316059
    Abstract: The present disclosure relates to a flexible nonvolatile ferroelectric memory device, a 1T-1R (1Transistor-1Resistor) flexible ferroelectric memory device, and a manufacturing method for the same.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 29, 2011
    Applicant: Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Jong-Hyun Ahn, Jonghyun Rho
  • Patent number: 7985995
    Abstract: The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO3), produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. The structure is formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. Such a layer may be used as the gate insulator of a MOSFET, or as a capacitor dielectric. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 26, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20110147723
    Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: SRI INTERNATIONAL
    Inventors: John Hodges, JR., Marc Rippen, Carl Biver, JR.
  • Patent number: 7948045
    Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: May 24, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yang Li, Insik Jin, Harry Liu, Song S. Xue, Shuiyuan Huang, Michael X. Tang
  • Patent number: 7932547
    Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: April 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 7829923
    Abstract: In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: November 9, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang, Xiaochun Zhu, Kangho Lee, Matthew Nowak
  • Patent number: 7816150
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a first ferroelectric film over a lower electrode, crystallizing the first ferroelectric film, forming a second ferroelectric film in an amorphous state over the first ferroelectric film so as to fill voids existing on a surface of the first ferroelectric film, and forming an upper electrode over the second ferroelectric film of the amorphous state, wherein the crystallizing step of the first ferroelectric film is conducted by a thermal annealing process at a temperature of 585° C. or higher.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: October 19, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ko Nakamura
  • Patent number: 7781813
    Abstract: A ferroelectric memory device is equipped with a ferroelectric capacitor having a first electrode, a second electrode, and a ferroelectric layer between the first and second electrodes, and the ferroelectric memory device includes: a wiring that is connected to one of the first electrode and the second electrode, wherein the wiring includes a first wiring layer composed of titanium nitride oriented along a <111> direction, and a second wiring layer formed on the first wiring and composed of titanium aluminum nitride orientated along a <111> direction.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: August 24, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Hiroaki Tamura, Shuji Tsuruta
  • Publication number: 20100073989
    Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.
    Type: Application
    Filed: November 25, 2009
    Publication date: March 25, 2010
    Inventor: Hee Bok KANG
  • Patent number: 7659562
    Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-soo Ko, Ju-hwan Jung, Yong-su Kim, Seung-bum Hong, Hong-sik Park
  • Patent number: 7645617
    Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: January 12, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Hee Bok Kang
  • Publication number: 20100001325
    Abstract: A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.
    Type: Application
    Filed: June 30, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Naoya Sashida
  • Patent number: 7605436
    Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: October 20, 2009
    Assignee: Fujitsu Limited
    Inventor: Masaomi Yamaguchi
  • Publication number: 20090173978
    Abstract: A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate electrode of the first FET and a second gate electrode of the second FET are formed on the dielectric film, and a drain electrode and a source electrode are formed on the semiconductor film. Under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween, and the ends of the semiconductor film that forms the channel are located inwardly of the ends of the back-gate electrode.
    Type: Application
    Filed: November 17, 2008
    Publication date: July 9, 2009
    Inventor: Yoshihisa KATO
  • Patent number: 7528428
    Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the (ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 5, 2009
    Assignee: Japan Science and Technology Agency
    Inventors: Satoshi Sugahara, Masaaki Tanaka
  • Publication number: 20090045447
    Abstract: Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate.
    Type: Application
    Filed: August 17, 2007
    Publication date: February 19, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Gurtej Sandhu, Bhaskar Srinivasan, John Smythe
  • Patent number: 7449346
    Abstract: A method of manufacturing a ferroelectric thin film with good crystallinity and improved surface roughness includes: forming on a substrate a metal nitride-based precursor layer containing one selected from the group consisting of TiN, ZrxTi(1-x)N (0<x<1), FeN, and NbN; forming on the metal nitride-based precursor layer a mixed gas atmosphere containing oxygen (O2) and one reactive gas selected from the group consisting of PbO(g), Bi2O3(g), and K2O(g); annealing the metal nitride-based precursor layer in the mixed gas atmosphere and forming a ferroelectric thin film containing one selected from the group consisting of PbTiO3, PbZrxTi(1-x)O3 (0<x<1), Bi2Ti2O7, Bi4Ti3O12, BiFeO3, and KNbO3.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Simon Buehlmann
  • Patent number: 7410812
    Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: August 12, 2008
    Assignee: Fujitsu Limited
    Inventor: Masaomi Yamaguchi
  • Patent number: 7408187
    Abstract: A transistor device includes a transparent substrate. A high K dielectric is formed on the transparent substrate and transferred onto a flexible substrate. An organic transistor is formed on the high K dielectric.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 5, 2008
    Assignee: Massachusetts Institute of Technology
    Inventors: Il-Doo Kim, Yong Woo Choi, Harry L. Tuller
  • Publication number: 20080173912
    Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.
    Type: Application
    Filed: November 16, 2007
    Publication date: July 24, 2008
    Inventors: Yoshinori KUMURA, Tohru Ozaki, Susumu Shuto, Yoshiro Shimojo, Iwao Kunishima
  • Publication number: 20080142859
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may forming a conductive layer on a substrate, patterning the conductive layer, forming at least one nanodot on the patterned conductive layer, and forming a thin film ferroelectric material on the at least one nanodot.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Qing Ma, Li-Peng Wang
  • Patent number: 7382013
    Abstract: To provide a dielectric thin with a high dielectric constant, a low leakage current, and stable physical properties and electrical properties and to provide a thin film capacitor or other thin film dielectric device with a high capacitance and high reliability and a method of production of the same, a dielectric thin film containing oxides such as barium strontium titanate expressed by the formula (BaxSr(1-x))aTiO3 (0.5<x?1.0, 0.96<a?1.00) and having a thickness of not more than 500 nm and a method of production of a thin film dielectric device including a step of annealing the dielectric thin film in an atmosphere of an oxidizing gas after forming a dielectric thin film on a conductive electrode.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: June 3, 2008
    Assignee: TDK Corporation
    Inventors: Kiyoshi Uchida, Kenji Horino, Hitoshi Saita
  • Patent number: 7309617
    Abstract: The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A reference layer of this type comprises two magnetically coupled layers having a different Curie temperature. When cooling from a temperature above the Curie temperature TC1 of the first layer in an external magnetic field, the magnetization of the second layer is oriented by a second-order phase transition along the field direction of the external magnetic field. Upon further cooling below the Curie temperature TC2 of the second layer, the latter is oriented antiparallel with respect to the first layer as a result of the antiferromagnetic coupling between the two layers.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: December 18, 2007
    Assignee: Infineon Technologies AG
    Inventors: Manfred Ruehrig, Ulrich Klostermann
  • Publication number: 20070252186
    Abstract: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may protrude through the top surface of the oxide after CMP, the spacers serve to prevent possible later shorting to the stack.
    Type: Application
    Filed: July 3, 2007
    Publication date: November 1, 2007
    Inventor: Lin Yang
  • Publication number: 20070235782
    Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.
    Type: Application
    Filed: June 1, 2007
    Publication date: October 11, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shinichi Fukada
  • Publication number: 20070228432
    Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.
    Type: Application
    Filed: January 9, 2007
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Ishihara, Kenji Maruyama, Tetsuro Tamura, Hiromasa Hoko
  • Patent number: 7276758
    Abstract: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below both ends of the floating gate; a ferroelectric substance interposed between the silicon substrate and the floating gate inside the tunnel oxide film; a diffusion barrier film enclosing the ferroelectric substance; a control gate formed on the substrate including the floating gate; a gate oxide film formed below the control gate; spacers formed on both lateral walls of the laminated floating gate and control gate including the tunnel oxide film and gate oxide film, respectively; and source/drain regions formed within the substrate surfaces on both sides of the control gate including the spacers, respectively.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: October 2, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 7262450
    Abstract: A MFS type field effect transistor includes a semiconductor layer, a PZT system ferroelectric layer formed on the semiconductor layer, a gate electrode formed on the PZT system ferroelectric layer, and an impurity layer composing a source or a drain, formed in the semiconductor layer. The PZT system ferroelectric layer includes Nb that replaces a Ti composition by 2.5 mol % or more but 40 mol % or less.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: August 28, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Kijima, Yasuaki Hamada
  • Patent number: 7227210
    Abstract: A method for fabricating a non-volatile memory device. The method includes providing a substrate, e.g., silicon. The method also includes forming an oxide layer overlying the substrate; and forming a buffer layer overlying the oxide layer. A ferroelectric material is formed overlying the substrate and is formed preferably overlying the buffer layer. The method also includes forming a gate layer overlying the ferroelectric material, where the gate layer is overlying a channel region. The method further includes forming first source/drain region adjacent to a first side of the channel region and a second source/drain region adjacent to a second side of the channel region. In other embodiments, the method can also include other steps.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: June 5, 2007
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Hong Koo Kim
  • Patent number: 7220601
    Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: May 22, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-won Hwang, I-hun Song, Geun-young Yeom, Seok-jae Chung
  • Patent number: 7220684
    Abstract: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 22, 2007
    Assignee: ROHM Co., Ltd.
    Inventors: Norikazu Nishiyama, Korekazu Ueyama, Yoshiaki Oku
  • Publication number: 20070111425
    Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
    Type: Application
    Filed: January 3, 2007
    Publication date: May 17, 2007
    Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
  • Patent number: 7183596
    Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: February 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
  • Publication number: 20070015325
    Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 18, 2007
    Inventors: Matthias Goldbach, Dongping Wu
  • Publication number: 20070007564
    Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.
    Type: Application
    Filed: March 9, 2006
    Publication date: January 11, 2007
    Inventors: Shigenori Hayashi, Riichiro Mitsuhashi
  • Patent number: 7098496
    Abstract: The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: August 29, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu