Abstract: A protection circuit for use with an electronic DSL component having a tip connection and a ring connection, the protection circuit including: a first unidirectional transient-voltage-suppression (TVS) diode, having a negative TVS breakdown voltage BDV and diode forward voltage DV clamp, connected between Vcc and the tip connection of the DSL component; a second unidirectional TVS diode, having a diode forward voltage DV, connected between the tip connection of the DSL component and a negative ground clamp node; a third unidirectional TVS diode, having a negative TVS breakdown voltage BDV and diode forward voltage DV clamp, connected between Vcc and the ring connection of the DSL component; and a fourth unidirectional TVS diode, having a diode forward voltage DV, connected between the ring connection of the DSL component and the negative ground clamp node.

Abstract: A method to integrate a vertical IMPATT diode in a planar process.

Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1?p?n and 2?n) of 1.59?Ap?3.26 and a full width at half maximum Fp (eV) (where 1?p?n and 2?n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1?q?m and 2?m?n), and the m photoelectric conversion layers each satisfy the relationship of Ap?Fp<Bq?Ap with respect to any one of the n light emission peaks.

Abstract: A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.

Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.

Abstract: A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substra

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.

Abstract: A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.

Abstract: A sensor device and a method of forming comprises a die pad receives a sensor device, such as a MEMS device. The MEMS device has a first coefficient of thermal expansion (CTE). The die pad is made of a material having a second CTE compliant with the first CTE. The die pad includes a base and a support structure with a CTE compliant with the first and second CTE. The die pad has a support structure that protrudes from a base. The support structure has a height and wall thickness which minimize forces felt by the die pad and MEMS device when the base undergoes thermal expansion or contraction forces from a header.

Abstract: An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

Abstract: An organic light emitting element includes an organic light emitting diode formed on a substrate, coupled to a transistor including a gate, a source and a drain and including a first electrode, an organic thin film layer and a second electrode; a photo diode formed on the substrate and having a semiconductor layer including a high-concentration P doping region, a low-concentration P doping region, an intrinsic region and a high-concentration N doping region; and a controller that controls luminance of light emitted from the organic light emitting diode, to a constant level by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photo diode.

Abstract: Example methods and apparatus for Antimonide-based backward diode millimeter-wave detectors are disclosed. A disclosed example backward diode includes a cathode layer adjacent to a first side of a non-uniform doping profile, and an Antimonide tunnel barrier layer adjacent to a second side of the spacer layer.

Abstract: A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate 11 that includes an N+ semiconductor layer 1, and an N? semiconductor layer 2; a P-type anode region 15 that is formed by selective impurity diffusion into an outer surface of the N? semiconductor layer 2; and an anode electrode 17 that is conducted to the anode region 15 through a contact region 17c in the anode region 15. The anode region 15 has a substantially rectangular outer edge of which four sides are adapted to be linear parts B2 and four vertices are adapted to be curved parts B1, and outside the contact region 17c, N-type non-diffusion corner regions 16 that extend along the curved parts B1 are respectively formed.

Abstract: An object is to provide a photoelectric conversion element with high conversion efficiency. In a photoelectric conversion element with a fine periodic structure on a light-receiving surface side, focus is given to the traveling direction of light that is reflected off another surface. The photoelectric conversion element may be given a structure in which a textured structure that reflects light to the other surface is provided, and light that travels from the light-receiving surface side to the other surface side is reflected so that a component that travels along the photoelectric conversion layer increases. By the distance traveled by the reflected light inside the photoelectric conversion layer increasing, the light that enters the photoelectric conversion element is more easily absorbed by the photoelectric conversion layer and less easily released from the light-receiving surface side, and a photoelectric conversion element with high conversion efficiency can be provided.

Abstract: A power semiconductor device according to the present invention, which has a termination structure in which a field plate is provided on an insulating film filled in a recessed region formed in a semiconductor substrate and includes a plurality of unit cells connected in parallel, includes: a gate wiring region in which gate wiring electrically connected to each gate electrode of the plurality of unit cells is provided; and a gate pad region electrically connected to the gate wiring region, wherein the gate wiring region is disposed on the insulating film filled in a recessed region formed in the semiconductor substrate.

Abstract: A homojunction type high-speed photodiode has an active area of greater than at least 50 microns (?m) or preferably greater than 60 microns (?m) in diameter, which has an p-i-n junction epitaxial layer formed on a semiconductor substrate and includes a first ohmic contact layer, an absorption layer, a collector layer and a second ohmic contact layer. No more absorbance occurs in the collector layer of InGaAs, by means of completely absorbing the photon energy in advance by the absorption layer in which the absorption layer has powerful optical absorption constant. Not only can the prior art problems be solved, such as surface absorbance, but also improved electron transport can be achieved by using InGaAs as the constructing material, compared to other materials. The resistance capacitance (RC) for the entire structure can be significantly reduced, and the limitations to the bandwidth resulted from the carrier transport time can be improved.

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material.

Abstract: An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.

Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array.

Abstract: A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate.

Abstract: Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier.

Abstract: A protective structure is produced by providing a semiconductor substrate having doping of a first conductivity type. A semiconductor layer having doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, producing a layer at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone having doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone having doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first and second regions of the semiconductor layer. A common connection device is formed for the first and second dopant zones.

Abstract: Provided is a PIN diode that can suppress thermal destruction from occurring at the time of a reverse bias exceeding a breakdown voltage by current concentration on a curved part of an anode region. The PIN diode is configured to have: a semiconductor substrate 11 that includes an N+ semiconductor layer 1 and an N? semiconductor layer 2; a cathode electrode 18 that is formed on an outer surface of the N+ semiconductor layer 1; a main anode region 16, a separated anode region 15, and an anode connecting region that are formed by selectively diffusing P-type impurities from an outer surface of the N? semiconductor layer 2; and an anode electrode 17 that is formed on the main anode region 16.

Abstract: A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate 11 that includes an N+ semiconductor layer 1, and an N? semiconductor layer 2; a P-type anode region 15 that is formed by selective impurity diffusion into an outer surface of the N? semiconductor layer 2; and an anode electrode 17 that is conducted to the anode region 15 through a contact region 17c in the anode region 15. The anode region 15 has a substantially rectangular outer edge of which four sides are adapted to be linear parts B2 and four vertices are adapted to be curved parts B1, and outside the contact region 17c, N-type non-diffusion corner regions 16 that extend along the curved parts B1 are respectively formed.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the first substrate; a second electrode electrically connected to the amplifier circuit and provided over an another end portion of the first substrate; and a second substrate having third and fourth electrodes thereon. The first and second electrodes are attached to the third and fourth electrodes, respectively, with a conductive material provided not only at the surfaces of the first, second, third, and fourth electrodes facing each other but also at the side surfaces of the first and second electrodes to increase the adhesiveness between a photoelectric conversion device and a member on which the photoelectric conversion device is mounted.

Abstract: This semiconductor device includes: a substrate; and a plurality of thin-film diodes which are supported by the substrate and electrically connected in parallel with each other. The thin-film diodes include at least one thin-film diode of a first type (100A), of which the semiconductor layer (10A) has an N-type region (1A), an intrinsic region (5A), and a P-type region (3A) that are arranged in this order in a first direction X within a plane that is parallel to the substrate, and at least one thin-film diode of a second type (100B), of which the semiconductor layer (10B) has a P-type region (3B), an intrinsic region (5B), and an N-type region (1B) that are arranged in this order in the first direction X. With such a configuration adopted, the variation in photocurrent characteristic between the thin-film diodes can be reduced.

Abstract: A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO2) layer between p- and n-doped regions as the natural resonator volume. Embodiments that do not include a metal ground plane and/or a metal patch are disclosed.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device.

Abstract: A transparent conductive film includes indium oxide containing hydrogen and cerium and having a substantially polycrystalline structure, in which specific resistance of the transparent conductive film is no greater than 3.4×10?4?·cm and the carrier mobility is no less than 70 cm2/Vs.

Abstract: A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode.

Abstract: A photoelectric conversion device includes a first electrode; and, over the first electrode, photoelectric conversion layer that includes a first semiconductor layer having one conductivity, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer. An insulating layer is over the third semiconductor layer, and a second electrode is over the insulating layer and is electrically connected to the third semiconductor layer through the insulating layer. The third semiconductor layer and a part of the second semiconductor layer are removed in a region of the photoelectric conversion layer that does not overlap the insulating layer.

Abstract: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.

Abstract: A manufacturing method of a photoelectric conversion device includes the following steps: forming a first electrode over a substrate; and, over the first electrode, forming a photoelectric conversion layer that includes a first conductive layer having one conductivity, a second semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer over the first electrode. The manufacturing method further includes the step of removing a part of the second semiconductor layer and a part of the third semiconductor layer in a region of the photoelectric conversion layer so that the third semiconductor layer does not overlap the first electrode.

Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands.

Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behavior is obtained that may be applicable in many fields.

Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.

Abstract: A power semiconductor device according to the present invention, which has a termination structure in which a field plate is provided on an insulating film filled in a recessed region formed in a semiconductor substrate and includes a plurality of unit cells connected in parallel, includes: a gate wiring region in which gate wiring electrically connected to each gate electrode of the plurality of unit cells is provided; and a gate pad region electrically connected to the gate wiring region, wherein the gate wiring region is disposed on the insulating film filled in a recessed region formed in the semiconductor substrate.