Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: In an integrated semiconductor optical device, a first cladding layer is made of a first conductivity type semiconductor. A first active layer for forming a first semiconductor optical device is provided on the first cladding layer in a first area of a principal surface of a substrate. A second active layer for forming a second semiconductor optical device is provided on the first cladding layer in a second area of the principal surface. A second cladding layer made of a second conductivity type semiconductor is provided on the second active layer. A third cladding layer made of a first conductivity type semiconductor is provided on the first active layer. A tunnel junction region is provided between the first active layer and the third cladding layer. The first active layer is coupled to the second active layer by butt joint. The second and third cladding layers form a p-n junction.

Abstract: A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: In an integrated semiconductor optical device, a first cladding layer is made of a first conductivity type semiconductor. A first active layer for forming a first semiconductor optical device is provided on the first cladding layer in a first area of a principal surface of a substrate. A second active layer for forming a second semiconductor optical device is provided on the first cladding layer in a second area of the principal surface. A second cladding layer made of a second conductivity type semiconductor is provided on the second active layer. A third cladding layer made of a first conductivity type semiconductor is provided on the first active layer. A tunnel junction region is provided between the first active layer and the third cladding layer. The first active layer is coupled to the second active layer by butt joint. The second and third cladding layers form a p-n junction.

Abstract: A memory cell includes a storage capacitor and a negative differential resistance (NDR) field effect transistor (FET), wherein the NDR FET is connected between a high voltage source and the storage capacitor. A junction between the NDR FET and the storage capacitor forms a storage node of the memory cell. when a logic HIGH value is stored at the storage node, a pulsed gate bias signal turns on the NDR FET. In contrast, when a logic LOW value is stored at the storage node, the pulsed gate bias signal does not turn on the NDR FET. Thus, using the NDR FET as a pull-up element, the memory cell can exhibit a refresh behavior that is dependent on the data value stored in the memory cell. Moreover, this memory cell can be operated without a separate refresh cycle.