Conductor-insulator-conductor Capacitor On Semiconductor Substrate (epo) Patents (Class 257/E29.343)
  • Patent number: 10811419
    Abstract: Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Devesh Dadhich Shreeram, Sanket S. Kelkar, Gurpreet S. Lugani, Paul A. Paduano, Matthew N. Rocklein, Sanjeev Sapra, Christopher W. Petz
  • Patent number: 9041153
    Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: May 26, 2015
    Assignee: BROADCOM CORPORATION
    Inventors: Xiangdong Chen, Henry Kuo-Shun Chen, Wei Xia, Bruce Chih-Chieh Shen
  • Patent number: 9035424
    Abstract: A semiconductor device includes a substrate, a metal film on a portion of the substrate, a first dielectric film having a first portion on the metal film and a second portion on the substrate, the second portion being integral with the first portion, a lower electrode on the first portion, a second dielectric film having a first portion on the lower electrode and a second portion on the first dielectric film, the second portion of the second dielectric film being integral with the first portion of said second dielectric film, an upper electrode on a portion of the second dielectric film, and a reinforcing film disposed on the second dielectric film and in contact with a side of the upper electrode.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 19, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masahiro Totsuka
  • Patent number: 9029187
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 12, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B Phatak
  • Patent number: 8980703
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Maxchip Electronics Corp.
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Patent number: 8963287
    Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Lei Tian, Scott W. Barry, Xuejun Ying
  • Patent number: 8957403
    Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
  • Patent number: 8932932
    Abstract: An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Johnathan E. Faltermeier, Anne Marie Kimball
  • Patent number: 8907449
    Abstract: Proposed are thin film MIM capacitors with which deterioration of insulating properties and leakage current properties can be sufficiently inhibited. Also proposed is a manufacturing method for the thin film MIM capacitors. For the thin film MIM capacitor (1), a lower electrode (3), a base metal thin film (4), the dielectric thin film (5) and the upper electrode (6) are formed to approximately the same area. The lower electrode (3) has a configuration that differs from the other films to form a part for external connection. The side surface of the base metal thin film (4), the dielectric thin film (5), and the upper electrode (6) are covered with a base metal oxide (7) that comprises the same metal atoms as the base metal thin film (4).
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: December 9, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Tomoyuki Takahashi, Kentarou Morito, Yuichi Sasajima, Yoshinari Take
  • Patent number: 8901706
    Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
  • Patent number: 8878340
    Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 4, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
  • Patent number: 8835251
    Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 16, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: YongZhong Hu, Sung-Shan Tai
  • Patent number: 8816474
    Abstract: One or more embodiments relate to a semiconductor device, comprising: a substrate; and a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andre Hanke, Oliver Nagy
  • Patent number: 8810000
    Abstract: A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8809999
    Abstract: A semiconductor integrated circuit device includes a lower electrode formed on a substrate, a first dielectric layer formed of a metal nitride layer, a metal oxynitride layer, or a combination thereof, on the lower electrode, a second dielectric layer formed on the first dielectric layer that includes a zirconium oxide layer, and an upper electrode formed on the second dielectric layer.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Min-Woo Song, Jung-Min Park
  • Patent number: 8791519
    Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Shuang Meng
  • Patent number: 8779548
    Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) including a plurality of circuit elements and a metallization stack (20) covering said substrate for providing interconnections between the circuit elements, wherein the top metallization layer of said stack carries a plurality of metal portions (30) embedded in an exposed porous material (40) for retaining a liquid, said porous material laterally separating said plurality of metal portions. An electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: July 15, 2014
    Assignee: NXP, B.V.
    Inventors: Youri Victorovitch Ponomarev, Aurelie Humbert, Roel Daamen
  • Patent number: 8772847
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8766346
    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Xiangxin Rui, Sergey Barabash
  • Patent number: 8753952
    Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Robert Summerfelt, John A. Rodriguez, Huang-Chun Wen, Steven Craig Bartling
  • Patent number: 8748283
    Abstract: Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 8742542
    Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Cheng Yang, Bo Tao, Jason Luo, Jinganag Wu
  • Patent number: 8735954
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8698221
    Abstract: A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiyeon Park, Insang Jeon, Hanjin Lim, Yeongcheol Lee, Jun-Noh Lee
  • Patent number: 8692355
    Abstract: A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Daisuke Tanaka, Hiroyoshi Ichikura
  • Publication number: 20140080283
    Abstract: A method of forming a semiconductor structure. The method comprises forming a high-k dielectric material, forming a continuous interfacial material over the high-k dielectric material, and forming a conductive material over the continuous interfacial material. Additional methods and semiconductor structures are also disclosed.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 20, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zhe Song, Jennifer K. Sigman
  • Patent number: 8674478
    Abstract: A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 ?m2 and L/S equal to or larger than 0.4 ?m?1, where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirotoshi Tachibana
  • Patent number: 8674423
    Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: David S. Collins, Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel
  • Patent number: 8659121
    Abstract: Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Kuo-Chyuan Tzeng, Wen-Chuan Chiang, Chen-Jong Wang
  • Publication number: 20140042590
    Abstract: Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ji Chen, Wen-Chuan Chiang, Huey-Chi Chu, Ming-Hsiang Song, Chen-Jong Wang
  • Publication number: 20140035099
    Abstract: Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Matthias Lehr
  • Publication number: 20140021584
    Abstract: Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chi Tu, Wen-Ting Chu
  • Publication number: 20140021583
    Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sut-I Lo, Ching-Wen Hsiao, Hsu-Hsien Chen, Chen-Shien Chen
  • Publication number: 20140008763
    Abstract: Capacitor device structures can be fabricated on a substrate including multiple separate first electrodes and a common distributed second electrode. The second electrode can be common to the multiple first electrodes and can be distributed in a shape of a grid interdigitating the multiple first electrodes. The distributed nature of the second electrode can replace the substrate backside as the bottom electrode and can reduce the device parasitic characteristics. In some embodiments, the capacitor device structures can be used in a high productivity combinatorial process, wherein the distributed nature of the second electrode can make the test structures more tolerant to misalignment.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Salil Mujumdar, Amol Joshi
  • Patent number: 8618633
    Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Badih El-Kareh
  • Patent number: 8614472
    Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 24, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Syed S. Islam, Mansour Keramat
  • Patent number: 8614497
    Abstract: According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 24, 2013
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen, Akira Ito
  • Patent number: 8609530
    Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 17, 2013
    Assignees: STMicroelectronics S.A., International Business Machines Corporation
    Inventors: Simon Jeannot, Pascal Tannhof
  • Publication number: 20130328167
    Abstract: A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Baozhen Li, Keith Kwong Hon Wong
  • Patent number: 8604586
    Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: December 10, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Wootag Kang, Jonghae Kim
  • Patent number: 8604587
    Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund Burke, Satyavolu Srinivas Papa Rao, Timothy Alan Rost
  • Patent number: 8592945
    Abstract: An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hak-Lay Chuang, Ming Zhu
  • Patent number: 8580648
    Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Kyung-Hyun Kim, Chang-Sup Mun, Sung-Jun Kim, Jin-I Lee
  • Patent number: 8581315
    Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: November 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoru Isogai, Takahiro Kumauchi
  • Patent number: 8575671
    Abstract: A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Hiroyuki Ode
  • Patent number: 8564094
    Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 8564095
    Abstract: Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. Capacitors, semiconductor devices and methods of forming a semiconductor device including the capacitors are also disclosed.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 8558228
    Abstract: A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu, Sally Liu
  • Patent number: 8552527
    Abstract: An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 8551857
    Abstract: The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 8, 2013
    Assignees: Hitachi, Ltd., Asahi Kasei Microdevices Corporation
    Inventors: Yuji Imamura, Tsuyoshi Fujiwara, Toyohiko Kuno