Abstract: A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L2, wherein an electrostatic capacity C1 of the first capacitance section and an electrostatic capacity C2 of the second capacitance section are different, and L1/L2=0.8 to 1.2.

Abstract: The present disclosure provides power semiconductor module, comprising at least three non-jumping power terminals at a non-jumping potential, wherein multiple power semiconductors and at least one first capacitor are integrated within a package and electrically connected between a first non-jumping power terminal and a second non-jumping power terminal of the at least three non-jumping power terminals; and at least one jumping power terminal at a jumping potential. A first jumping power terminal of the at least one jumping power terminal is electrically connected to one terminal of a power inductor and a third non-jumping power terminal of the at least three non-jumping power terminals is electrically connected to the other terminal of the power inductor; wherein at least one second capacitor is electrically connected between the third non-jumping power terminal and at least one of other non-jumping power terminals.

Abstract: A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

Abstract: A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors.

Abstract: An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.

Abstract: A dielectric thin film element that includes a substrate, a close-adhesion layer formed on one principal surface of the substrate, a capacitance section having a lower electrode layer formed on the close-adhesion layer, a dielectric layer formed on the lower electrode layer, and an upper electrode layer formed on the dielectric layer, and a protective layer formed to cover the capacitance section, wherein the end of the close-adhesion layer is exposed from the protective layer.

Abstract: An organic light emitting diode display includes a substrate; a first capacitor electrode provided over the substrate and including polysilicon; an insulating layer provided over the first capacitor electrode; and a second capacitor electrode provided over the insulating layer and including a first lower metal layer overlapping with the first capacitor electrode and a first upper metal layer. The first upper metal layer includes a doping opening configured to expose at least a portion of the first lower metal layer.

Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.

Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.

Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.

Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor dopant incorporated within the dielectric layer. The oxygen donor dopants may be incorporated within the dielectric layer during the formation of the dielectric layer. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.

Abstract: A device includes a top metal layer over a substrate; a copper-containing metal feature in the top metal layer; a passivation layer over the top metal layer; and a capacitor. The capacitor includes a bottom electrode including at least a portion in the first passivation layer, wherein the bottom electrode includes aluminum; an insulator over the bottom electrode; and a top electrode over the insulator.

Abstract: A method of manufacturing a semiconductor device includes: forming a core insulating film that includes first openings, on a semiconductor substrate; forming cylindrical lower electrodes that cover sides of the first openings with a conductive film; forming a support film that covers at least an upper surface of the core insulating film between the lower electrodes; forming a mask film in which an outside of a region where at least the lower electrodes are formed is removed, by using the support film; and performing isotropic etching on the core insulating film so as to leave the core insulating film at a part of an area between the lower electrodes, after the mask film is formed.

Abstract: A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.

Abstract: Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.

Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.

Abstract: An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate, a patterned semiconductor substrate, having at least one opening, disposed on the glass substrate and at least one passive component having a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate.

Abstract: An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.

Abstract: In one aspect, a memory cell capacitor is provided. The memory cell capacitor includes a silicon wafer; at least one trench in the silicon wafer; a silicide within the trench that serves as a bottom electrode of the memory cell capacitor, wherein a contact resistance between the bottom electrode and the silicon wafer is from about 1×10?6 ohm-cm2 to about 1×10?9 ohm-cm2; a dielectric in the trench covering the bottom electrode; and a top electrode in the trench separated from the bottom electrode by the dielectric.

Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.

Abstract: One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract: A high-voltage metal capacitor with easy integration into existing semiconductor manufacturing processes can provide isolation capacitors up to several kilovolts. The capacitor includes a support layer with internal structure, including a lower place, a bond pad on the support layer, an upper plate disposed on the support layer, the upper plate being arranged above the lower plate, a dielectric layer, at least part of which is between the lower and upper plates, and a passivation layer, at least part of which covers at least part of the upper plate and part of the dielectric layer. A first opening extends from the surface through the passivation and dielectric layers to the lower plate, and a second opening extends from the surface through the passivation layer to the upper plate. A method of manufacturing the capacitor.

Abstract: A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.

Abstract: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.

Abstract: Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

Abstract: A capacitor structure includes a first conductive structure, a dielectric structure, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode. The first conductive structure is disposed over a substrate. The dielectric structure is disposed over the substrate and partially enclosing the first conductive structure. The dielectric structure has a trench. A first surface of the first conductive structure is exposed through the trench of the dielectric structure. The first capacitor electrode is disposed on a bottom and a sidewall of the trench. The first capacitor electrode is electrically contacted with the first surface of the first conductive structure. The capacitor dielectric layer is disposed on a surface of the first capacitor electrode. The second capacitor electrode is disposed on a surface of the capacitor dielectric layer and filled in the trench.

Abstract: The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR).

Abstract: In various embodiments, a capacitor arrangement is provided, which may include a substrate; a plurality of first doped regions and a plurality of second doped regions, wherein the first doped regions are doped with dopants of a first conductivity type and the second doped regions are doped with dopants of a second conductivity type being opposite to the first conductivity type, and wherein the plurality of first doped regions and the plurality of second doped regions are alternatingly arranged next to each other in the substrate; a dielectric layer disposed over the plurality of first doped regions and the plurality of second doped regions; an electrode disposed over the dielectric layer; a first terminal electrically coupled to each doped region of the plurality of first doped regions and the plurality of second doped regions; and a second terminal electrically coupled to the electrode.

Abstract: A semiconductor device includes: a substrate configured to include cell regions and a peripheral region around the cell regions; storage nodes arranged in each of the cell regions; a first support pattern configured in each cell region to support the storage nodes; and a second support pattern configured in the peripheral region to couple first support patterns to each other.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.

Abstract: A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer. a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.

Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.

Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.

Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

Abstract: A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars.

Abstract: An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.

Abstract: The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well serve as the isolation structures. The low voltage control circuit is located outside the deep N well and the floating circuit is located inside the deep N well. The deep N well forms a high voltage junction barrier for isolating the control circuit from the floating circuit.

Abstract: A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.

Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Abstract: Embodiments of the present invention generally relate to methods and apparatus for forming an energy storage device. More particularly, embodiments described herein relate to methods of forming electric batteries and electrochemical capacitors. In one embodiment a method of forming a high surface area electrode for use in an energy storage device is provided. The method comprises forming an amorphous silicon layer on a current collector having a conductive surface, immersing the amorphous silicon layer in an electrolytic solution to form a series of interconnected pores in the amorphous silicon layer, and forming carbon nanotubes within the series of interconnected pores of the amorphous silicon layer.

Abstract: Circuits for shielding devices from electromagnetic coupling with through-silicon vias are shown that include a substrate having a through via, which provides access to a device layer on a first surface of the circuit to a device layer on a second surface of the circuit; a conductive layer on the first side of the substrate; a contact point on one of the device layers; and a grounded buried interface tie on the conductive layer, adjacent to the contact point, to isolate the contact point from coupling noise.

Abstract: A method of forming a semiconductor device includes forming an opening having a sidewall in a substrate and forming a first epitaxial layer in the opening. The first epitaxial layer is formed in a first portion of the sidewall without growing in a second portion of the sidewall. A second epitaxial layer is formed in the opening after forming the first epitaxial layer. The second epitaxial layer is formed in the second portion of the sidewall. The first epitaxial layer is removed after forming the second epitaxial layer.

Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.