Variable Capacitance Diode (e.g., Varactors) (epo) Patents (Class 257/E29.344)
  • Patent number: 10917132
    Abstract: A switchless transceiver module is disclosed. In one or more embodiments, the transceiver module includes at least a first port, a second port, and a third port. The first port is configured to be coupled to an antenna. The transceiver module further includes a low-noise amplifier (LNA) configured to receive incoming signals from the antenna in a receiving mode of operation. The second port is coupled to an output of the LNA. The transceiver module further includes a power amplifier (PA) configured to transmit outgoing signals to the antenna in a transmitting mode of operation. The third port is coupled to an input of the PA. In embodiments, the input of the LNA and the output of the PA are configured to provide isolation in the receiving mode of operation or the transmitting mode of operation based on impedance matching.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 9, 2021
    Assignee: Rockwell Collins, Inc.
    Inventor: Russell D. Wyse
  • Patent number: 8957468
    Abstract: A variable capacitor with high controllability and stable operation is provided. A liquid crystal display device with low power consumption and excellent display quality is provided. A variable capacitor is formed using two overlapping electrodes of different areas and a substantially intrinsic semiconductor layer formed in contact with one of the electrodes. According to the voltage applied to the electrodes, the semiconductor layer can be considered as a dielectric or a conductor, thereby allowing varying the capacitance of the variable capacitor. The variable capacitor is applied to pixels of a liquid crystal display device configured to switch between a low capacitance and a high capacitance of the variable capacitor in accordance with a moving image display mode and a still image display mode, respectively, whereby a liquid crystal display device with low power consumption and excellent display quality can be realized.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Uochi
  • Patent number: 8941212
    Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 8878340
    Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 4, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
  • Patent number: 8796809
    Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: August 5, 2014
    Assignee: Cree, Inc.
    Inventor: Christopher Harris
  • Publication number: 20140124893
    Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Josef Dietl, Raimund Peichl, Gabriele Bettineschi
  • Patent number: 8614472
    Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 24, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Syed S. Islam, Mansour Keramat
  • Patent number: 8598683
    Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Edward J. Nowak
  • Publication number: 20130313683
    Abstract: Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: Oki Gunawan, Amlan Majumdar, Katherine L. Saenger
  • Patent number: 8558350
    Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
  • Patent number: 8531006
    Abstract: A memory capacitor based on a field configurable ion-doped polymer is reported. The device can be dynamically and reversibly programmed to analog capacitances with low-voltage (<5 V) pulses. After the device is programmed to a specific value, its capacitance remains nonvolatile. The field configurable capacitance is attributed to the modification of ionic dopant concentrations in the polymer. The ion and dipole concentrations in the ion conductive layer can be modified when the voltage biases applied to the electrodes exceeds a threshold value and can operate as a conventional capacitor when a voltage less than the threshold value is applied. The ion conductive layer will remain at a stable value after the device is modified without applying external voltage. The device has a nonvolatile memory function even when the external voltage is turned off. The memory capacitors may be used for analog memory, nonlinear analog and neuromorphic circuits.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: September 10, 2013
    Assignee: The Regents of the University of California
    Inventor: Yong Chen
  • Patent number: 8530948
    Abstract: In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: September 10, 2013
    Assignee: Blackberry Limited
    Inventors: Xubai Zhang, Louise C. Sengupta, Jason Sun, Nicolass DuToit
  • Publication number: 20130200494
    Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.
    Type: Application
    Filed: February 5, 2012
    Publication date: August 8, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Zhiying CHEN, Jianping ZHAO, Lee CHEN, Merritt FUNK, Radha SUNDARARAJAN
  • Patent number: 8502348
    Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yue-Shiun Lee, Cheng-Hsiung Chen, Meng-Fan Wang
  • Patent number: 8492823
    Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Nowak
  • Patent number: 8450832
    Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manju Sarkar, Purakh Raj Verma
  • Publication number: 20130119449
    Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ji CHEN, Wei Yu MA, Ta-Pen GUO, Hsien-Wei CHEN, Hao-Yi TSAI
  • Publication number: 20130113081
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ZHIHONG CHEN, SHU-JEN HAN, SIYURANGA O. KOSWATTA, ALBERTO VALDES GARCIA
  • Publication number: 20130100090
    Abstract: This disclosure provides systems, methods and apparatus for electromechanical systems variable capacitance devices. In one aspect, an electromechanical systems variable capacitance device includes a substrate with a first metal layer including a first bias electrode overlying the substrate. A member suspended above the first metal layer includes a dielectric beam and a second metal layer including a first radio frequency electrode and a ground electrode. The member and the first metal layer define a first air gap. A third metal layer over the member includes a second bias electrode, and the third metal layer and the member define a second air gap. The member includes a plane of symmetry substantially parallel a plane containing the first bias electrode.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Daniel FELNHOFER, Wenyue ZHANG, Je-Hsuing LAN
  • Publication number: 20130049646
    Abstract: An energy conversion device, and methods of manufacturing and operating the same. The energy conversion device includes: a monolithic single-crystal silicon layer that includes a plurality of doping regions; a vibrator that is disposed in the single-crystal silicon layer and is connected to a doping region of the plurality of doping regions; a first diode that is a PN junction diode and allows an input signal applied to the vibrator to pass therethrough; and a second diode that is a PN junction diode and allows a signal output from the vibrator to pass therethrough.
    Type: Application
    Filed: June 19, 2012
    Publication date: February 28, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Che-heung KIM, Jong-oh KWON
  • Patent number: 8378453
    Abstract: Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: February 19, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
  • Patent number: 8362591
    Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Hsien-Pin Hu, Jhe-Ching Lu, Chin-Wei Kuo, Ming-Fa Chen, Sally Liu
  • Publication number: 20130009228
    Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 10, 2013
    Inventors: Yue-Shiun Lee, Cheng-Hsiung Chen, Meng-Fan Wang
  • Publication number: 20120319176
    Abstract: In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung CHEN, Chewn-PU JOU, Chin Wei KUO, Sally LIU
  • Patent number: 8334571
    Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20120235731
    Abstract: A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 20, 2012
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Bin Li, Peter J. Zampardi, JR., Andre G. Metzger
  • Publication number: 20120205781
    Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES INCORPORATED
    Inventors: David M. Fried, Edward J. Nowak
  • Patent number: 8242581
    Abstract: Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: August 14, 2012
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Wilson Wong, Jun Liu, Qi Xiang, Jeffrey Xiaoqi Tung
  • Patent number: 8232624
    Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Joseph E. Nowak
  • Patent number: 8217496
    Abstract: An internal matching transistor comprises: a conductive base material including a groove, a first region, and a second region which is located opposite to the first region across the groove; a transistor bonded onto the first region of the base material; an internal matching circuit bonded onto the second region of the base material; a wire connecting the transistor to the internal matching circuit across above the groove; and a conductive or non-conductive material located between the wire and the groove, wherein capacitance between the wire and the base material is adjusted by the material.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 10, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiromitsu Utsumi
  • Patent number: 8217489
    Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode, a variable resistance layer, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes. The variable resistance layer includes at least a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx; and wherein when a resistance value between the electrodes is in the low-resistance state is RL, a resistance value between the electrodes is in the high-resistance state is RH, and a resistance value of a portion other than the variable resistance layer in a current path connecting a first terminal to a second terminal via the first electrode, the variable resistance layer and the second electrode, is R0, R0 satisfies RL<R0.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Koichi Osano, Satoru Fujii, Shunsaku Muraoka
  • Patent number: 8217497
    Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bradley A. Orner, Edward J. Nowak, Robert M. Rassel
  • Publication number: 20120146188
    Abstract: A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 14, 2012
    Inventors: Fan Chen, Xiongbin Chen
  • Publication number: 20120113341
    Abstract: A variable capacitor with high controllability and stable operation is provided. A liquid crystal display device with low power consumption and excellent display quality is provided. A variable capacitor is formed using two overlapping electrodes of different areas and a substantially intrinsic semiconductor layer formed in contact with one of the electrodes. According to the voltage applied to the electrodes, the semiconductor layer can be considered as a dielectric or a conductor, thereby allowing varying the capacitance of the variable capacitor. The variable capacitor is applied to pixels of a liquid crystal display device configured to switch between a low capacitance and a high capacitance of the variable capacitor in accordance with a moving image display mode and a still image display mode, respectively, whereby a liquid crystal display device with low power consumption and excellent display quality can be realized.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 10, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hideki Uochi
  • Patent number: 8125021
    Abstract: A non-volatile memory device includes a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an alloy thereof, the second oxide layer is a transition metal oxide, the buffer layer is composed of a p-type oxide and the upper electrode is composed of a material selected from Ni, Co, Cr, W, Cu or an alloy thereof.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Rae Cho, Eun-Hong Lee, El Mostafa Bourim, Chang-Wook Moon
  • Patent number: 8115281
    Abstract: A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: February 14, 2012
    Assignee: Atmel Corporation
    Inventors: Adam H. Pawlikiewicz, Samir el Rai
  • Publication number: 20120032304
    Abstract: It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer from being attached to a substrate after the sacrifice layer etching. In other words, an object of the present invention is to provide an inexpensive and high-value-added micromachine by improving throughput and yield. The sacrifice layer etching is conducted in multiple steps. In the multiple steps of the sacrifice layer etching, a part of the sacrifice layer that does not overlap with the structural layer is removed by the earlier sacrifice layer etching and a part of the sacrifice layer that is under the structural layer is removed by the later sacrifice layer etching.
    Type: Application
    Filed: October 18, 2011
    Publication date: February 9, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mayumi Yamaguchi, Konami Izumi
  • Publication number: 20110298551
    Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Tsung YEN, Hsien-Pin HU, Jhe-Ching LU, Chin-Wei KUO, Ming-Fa CHEN, Sally LIU
  • Publication number: 20110278700
    Abstract: An internal matching transistor comprises: a conductive base material including a groove, a first region, and a second region which is located opposite to the first region across the groove; a transistor bonded onto the first region of the base material; an internal matching circuit bonded onto the second region of the base material; a wire connecting the transistor to the internal matching circuit across above the groove; and a conductive or non-conductive material located between the wire and the groove, wherein capacitance between the wire and the base material is adjusted by the material.
    Type: Application
    Filed: February 11, 2011
    Publication date: November 17, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hiromitsu UTSUMI
  • Patent number: 8053866
    Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: November 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Reuda, Vishal P. Trivedi
  • Publication number: 20110260293
    Abstract: Provided is a variable capacitance device including a nanomaterial layer made of a plurality of kinds of nanomaterials having characteristics different from each other, a first conductive layer electrically connected to at least a part of the nanomaterial layer, and a second conductive layer facing the nanomaterial layer and the first conductive layer through an insulating film.
    Type: Application
    Filed: July 22, 2009
    Publication date: October 27, 2011
    Inventor: Kaoru Narita
  • Patent number: 8039922
    Abstract: When a positive voltage of V1 is applied to a drive capacitor with a braking voltage V2 at 0V, a moveable electrode moves toward the drive electrode, and a capacitance C of a tunable capacitor becomes smaller. When the braking voltage V2 is applied a lower portion brake electrode of the brake capacitor moves in a horizontal direction, such that the inter electrode separation distance between an upper portion brake electrode and the lower portion brake electrode becomes 0 ?m. The moveable electrode configured integrally formed with the lower portion brake electrode also moves in the horizontal direction, and the inter electrode separation distance between the moveable electrode and a fixed electrode becomes 0 ?m. Since the two electrodes make contact with each other with a dielectric layer interposed therebetween, the position of the moveable electrode can be stably maintained by frictional force between the electrodes.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: October 18, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Wei Ni
  • Publication number: 20110233678
    Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsien TSAI, Tzu-Jin YEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Patent number: 8013379
    Abstract: The semiconductor variable capacitor includes a capacitor including an n-well 16 formed in a first region of a semiconductor substrate 10, an insulating film 18 formed over the semiconductor substrate 10 and a gate electrode 20n formed above the n-well 16 with the insulating film 18 interposed therebetween; and a p-well 14 of a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate 10. The gate electrode 20n has an end which is extended to the second region and formed above the p-well 14 with the insulating film 18 interposed therebetween.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toshiro Futatsugi
  • Publication number: 20110204969
    Abstract: Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 25, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung CHEN, Chewn-Pu Jou, Chin Wei Kuo, Sally Liu
  • Patent number: 7989302
    Abstract: Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Alvin J. Joseph, Robert M. Rassel, Yun Shi
  • Patent number: 7989922
    Abstract: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Randy W. Mann, Jae-Eun Park, Richard A. Wachnik
  • Patent number: 7989868
    Abstract: A MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, includes: gate insulating layers arranged at equal intervals in the form of a (n×m) matrix, and a gate electrode placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire, which is electrically connected to the gate contact; source/drain contacts arranged at equal intervals in a matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire, which is electrically connected to the source/drain contacts.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: August 2, 2011
    Assignee: Korea University Industrial & Academic Collaboration Foundation
    Inventors: Jae-Sung Rieh, Yong Ho Oh, Sue Yeon Kim, Seung Yong Lee
  • Publication number: 20110149374
    Abstract: A two-terminal, variable capacitance device is described that is constructed by connecting multiple MEMS devices having different actuation or “pull in” voltages in parallel.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Je-Hsiung Lan, Evgeni Gousev, Ernest Tadashi Ozaki
  • Publication number: 20110140240
    Abstract: An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 16, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Vishal P. Trivedi