Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: A memory capacitor based on a field configurable ion-doped polymer is reported. The device can be dynamically and reversibly programmed to analog capacitances with low-voltage (<5 V) pulses. After the device is programmed to a specific value, its capacitance remains nonvolatile. The field configurable capacitance is attributed to the modification of ionic dopant concentrations in the polymer. The ion and dipole concentrations in the ion conductive layer can be modified when the voltage biases applied to the electrodes exceeds a threshold value and can operate as a conventional capacitor when a voltage less than the threshold value is applied. The ion conductive layer will remain at a stable value after the device is modified without applying external voltage. The device has a nonvolatile memory function even when the external voltage is turned off. The memory capacitors may be used for analog memory, nonlinear analog and neuromorphic circuits.

Abstract: MEMS varactors capable of handling large signals and/or achieving a high capacitance tuning range are described. In an exemplary design, a MEMS varactor includes (i) a first bottom plate electrically coupled to a first terminal receiving an input signal, (ii) a second bottom plate electrically coupled to a second terminal receiving a DC voltage, and (iii) a top plate formed over the first and second bottom plates and electrically coupled to a third terminal. The DC voltage causes the top plate to mechanically move and vary the capacitance observed by the input signal. In another exemplary design, a MEMS varactor includes first, second and third plates formed on over one another and electrically coupled to first, second and third terminals, respectively. First and second DC voltages may be applied to the first and third terminals, respectively. An input signal may be passed between the first and second terminals.

Abstract: The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4) that encloses at least a portion of the dielectric layer (5). Preferably the nanowire (2) protrudes from a substrate (12). The gate electrode (4) defines a gated portion (7) of the nanowire (2), which is allowed to be fully depleted when a first predetermined voltage is applied to the gate electrode (4). A method for providing a variable capacitance in an electronic circuit by using such an nanostructured MOS capacitor is also provided. Thanks to the invention it is possible to provide a MOS capacitor having an increased capacitance modulation range. It is a further advantage of the invention to provide a MOS capacitor which has relatively low depletion capacitance compared to prior art MOS capacitances.

Abstract: A varactor element having a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element. The varactor element has an exponential depletion capacitance-voltage relation, e.g. obtained by providing a predetermined doping profile in the junction region. The varactor element can be used in a narrow tone spacing varactor stack arrangement, in which two varactor elements are connected in an anti-series configuration. A low impedance path for base band frequency components between a control node and each of two RF connection nodes is provided, while for fundamental and higher order harmonic frequencies, a high impedance path is provided.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: The present invention relates to a MEMS, being developed for e.g. a mobile communication application, such as switch, tunable capacitor, tunable filter, phase shifter, multiplexer, voltage controlled oscillator, and tunable matching network. The volume change of phase-change layer is used for a bi-stable actuation of the MEMS device. The MEMS device comprises at least a bendable cantilever, a phase change layer, and electrodes. A process to implement this device and a method for using is given.

Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).

Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Abstract: Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor.

Abstract: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.

Abstract: On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

Abstract: Disclosed are one-port and two-port microelectromechanical structures including variable capacitors, switches, and filter devices. High aspect-ratio micromachining is used to implement low-voltage, large value tunable and fixed capacitors, and the like. Tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 240 percent of tuning. Exemplary microelectromechanical apparatus comprises a single crystalline silicon substrate, and a conductive structure laterally separated from the single crystalline silicon substrate by first and second high aspect ratio gaps of different size, wherein at least one of the high aspect ratio gaps has an aspect ratio of at least 30:1, and is vertically anchored to the single crystalline silicon substrate by way of silicon nitride.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: The present invention has provided a new diode and transistor by employing the characteristic of the tunnel diode. The new diode and transistor are field interacted and can be a solarcell, light sensor, thermal device, Hall device, pressure device or acoustic device which outputs self-excited multi-band waveforms with broad bandwidth. The present invention has also revealed a precisional switch which can works at high speeds and a capacitor whose capacitance can be actively controlled.

Abstract: A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device.

Abstract: The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type.

Abstract: Disclosed is a varactor and/or variable capacitor. The varactor/variable capacitor includes a plurality of first conductive-type wells vertically formed on a substrate, a plurality of second conductive-type ion implantation areas formed in the first conductive-type wells, at least one second conductive-type plug electrically connected to the second conductive-type ion implantation areas, an isolation layer formed at sides of an uppermost second conductive-type ion implantation area, and a first conductive-type ion implantation area in an uppermost first conductive-type well electrically disconnected from the uppermost second conductive-type ion implantation area by the isolation area.

Abstract: Varactor shunt switches based on a nonlinear dielectric tunability of BaxSr(1?x)TiO3 (BST) thin-film on a sapphire substrates are presented. Nanostructured BST thin-films with dielectric tunability as high as 4.3:1 can be obtained on sapphire substrates, with very low loss-tangents below 0.025 at zero-bias and 20 GHz. The large capacitance of the varactor at zero bias can shunt the input signal to ground isolating the output port, resulting in the OFF state. When applying a bias voltage of approximately 10 V (a dc electric field of ˜250 kV/cm), the varactor's capacitance can be reduced to a minimum, allowing maximum transmission to the output resulting in the ON state. The microwave switching performance of the varactor shunt switch can be compared with the RF MEMS switches for potential applications at microwave and millimeterwave frequencies.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (70) having a first surface (73) and in which are formed a first N region (46) having a first peak dopant concentration (47) located at a first depth (48) beneath the surface (73), and a first P region having a second peak dopant concentration (50) greater than the first peak dopant concentration located at a second depth (51) beneath the surface less than the first depth (48), and a second P region (42) having a third peak dopant concentration (43) greater than the second peak dopant concentration and located at a third depth at or beneath the surface (73) less than the second depth (51), so that the first P region (49) provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge (44) of the second P region (42) up to the second peak dopant concentration (50).

Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer.

Abstract: A capacitance arrangement comprising at least one parallel-plate capacitor comprising a first electrode means, a dielectric layer and a second electrode means partly overlapping each other. A misalignment limit is given. Said first electrode means comprises a first and a second electrode arranged symmetrically with respect to a longitudinal axis, said first and second electrodes have a respective first edge, which face each other, are linear and parallel such that a gap is defined there between. Said second electrode means comprises a third electrode with a first section and a second section disposed on opposite sides of said gap interconnected by means of an intermediate section, which is delimited by a function depending on a first parameter and a second parameter. One of said two parameters is adapted to be selected hence allowing calculation of the other parameter to determine the shape and size of the second electrode means.

Abstract: Disclosed is a method for detecting properties of a Metal Oxide Silicon (MOS) varactor, which includes: establishing a MOS varactor model equation in conjunction with an area of a gate; calculating values of the coefficients of the MOS varactor model equation through measurements for test materials; and extracting the properties of a capacitor of the MOS varactor using the calculated values of the coefficients. According to the method, the MOS varactor model equation can be expressed by Cgate=[Cigate×Area+Cpgate×Perimeter]×N, wherein, Cgate denotes gate capacitance for voltage applied to the gate, Cigate denotes intrinsic gate capacitance, Cpgate denotes perimeter gate capacitance, and N denotes the number of gate fingers. The MOS varactor model equation can be applicable to various sized capacitors, so that it is possible to estimate a gate capacitance for voltage applied to a gate, considering the differences due to the surface shapes of a device.

Abstract: A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.

Abstract: Nano-electromechanical device having an electrically conductive nano-cantilever wherein the nano-cantilever has a free end that is movable relative to an electrically conductive substrate such as an electrode of a circuit. The circuit includes a power source connected to the electrode and to the nano-cantilever for providing a pull-in or pull-out voltage therebetween to effect bending movement of the nano-cantilever relative to the electrode. Feedback control is provided for varying the voltage between the electrode and the nano-cantilever in response to the position of the cantilever relative to the electrode. The device provides two stable positions of the nano-cantilever and a hysteresis loop in the current-voltage space between the pull-in voltage and the pull-out voltage.

Abstract: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.

Abstract: A field effect transistor includes a silicon substrate, a source electrode and a drain electrode which are formed in upper portions of the silicon substrate, and an insulator film, a PCMO film, and a gate electrode which are formed on part of the silicon substrate sandwiched between the source electrode and the drain electrode. Data writing is performed by changing a voltage level of a write voltage applied to the PCMO film, and data reading is performed by applying a read voltage to the PCMO film and detecting a drain current.

Abstract: One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.

Abstract: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.

Abstract: Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

Abstract: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

Abstract: A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

Abstract: A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

Abstract: In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: A varactor comprising a first layer separated from a second layer by an insulating layer, wherein the first layer is a first type of semiconductor material and the second layer is a second type of semiconductor material and the insulation layer is arranged to allow an accumulation region to be formed in the first layer and second layer when a positive bias is applied to the first layer and the second layer and a depletion region to be formed in the first layer and second layer when a negative bias is applied to the first layer and the second layer.

Abstract: A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage.

Abstract: A varactor element having a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element. The varactor element has an exponential depletion capacitance-voltage relation, e.g. obtained by providing a predetermined doping profile in the junction region. The varactor element can be used in a narrow tone spacing varactor stack arrangement, in which two varactor elements are connected in an anti-series configuration. A low impedance path for base band frequency components between a control node and each of two RF connection nodes is provided, while for fundamental and higher order harmonic frequencies, a high impedance path is provided.

Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.

Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of CO, CO2, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of to 1000.