Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.

Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.

Abstract: A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench.

Abstract: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of the capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of trenches and the doped area for electrically insulating the trenches from the doped area. The doped area includes first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area.

Abstract: Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench.

Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.

Abstract: Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.

Abstract: A semiconductor device includes an isolation region, a semiconductor region, a groove, and an insulating film. The semiconductor region is defined by the isolation region. The groove is in the semiconductor region. The groove has first and second ends. At least one of the first and second ends reaches the isolation region. The insulating film is in the groove.

Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer located under the base region and extending to a depth deeper than the trench. The deep layer is formed into a lattice pattern.

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Abstract: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

Abstract: Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide layer in the first trench; a third oxide layer on the semiconductor substrate and on inner surfaces of the second and third trenches; and a polysilicon layer on the third oxide layer to fill the second and third trenches.

Abstract: This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.

Abstract: A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.

Abstract: The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.

Abstract: By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm?3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

Abstract: A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

Abstract: A trench structure and a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

Abstract: A semiconductor device and production method is disclosed. In one embodiment, the semiconductor device includes a first electrode and a second electrode, located on surfaces of a semiconductor body, and an insulated gate electrode. The semiconductor body has a contact groove for the first electrode in an intermediate oxide layer. Highly doped zones of a first conduction type are located in edge regions of the source connection zone. Below the highly doped zones of the first conduction type, there are highly doped zones of a body zone with a complementary conduction type. In a central region of the source connection zone, the body zone has a net charge carrier concentration with a complementary conduction type which is lower than the charge carrier concentration in the edge regions of the source connection zone.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

Abstract: A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.

Abstract: A design structure of a trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The design structure resulting from the means for fabricating the trench capacitor includes the methods of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon.

Abstract: An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n?-type drift layer to extend into the n?-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.

Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.

Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.

Abstract: A pair of through substrate vias is formed through a stack including a lightly doped semiconductor and a bottom semiconductor layer in a semiconductor substrate. The top semiconductor layer includes semiconductor devices such as field effect transistors. At least one deep trench is formed on the backside of the semiconductor substrate in the bottom semiconductor layer and at least one dielectric layer thereupon. A node dielectric and a conductive inner electrode are formed in each of the at least one deep trench. Substrate contact vias abutting the bottom semiconductor layer are also formed in the at least one dielectric layer. Conductive wiring structures on the backside of the semiconductor substrate provide lateral connection between the through substrate vias and the at least one conductive inner electrode and the substrate contact vias.

Abstract: A capacitor structure includes: a number of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in a trench structure of a semiconductor device; and a dielectric surrounding the conductive regions.

Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.

Abstract: A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.

Abstract: A capacitor device includes a substrate, a first conductive structure, a second conductive structure, a dielectric layer structure, and a recess in the substrate. The first and second conductive structures are disposed on opposite sides of the dielectric layer structure, and the dielectric layer structure extends in a meander-shaped manner in a cross-section through the recess.

Abstract: Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (<200 ng/?Hz) and very high sensitivity (>17 pF/g). The microstructures are fabricated in thick (>100 ?m) silicon-on-insulator (SOI) substrates or silicon substrates using a two-mask fully-dry release process that provides large seismic mass (>10 milli-g), reduced capacitive gaps, and reduced in-plane stiffness. Fabricated devices may be interfaced to a high resolution switched-capacitor CMOS IC that eliminates the need for area-consuming reference capacitors. The measured sensitivity is 83 mV/mg (17 pF/g) and the output noise floor is ?91 dBm/Hz at 10 Hz (corresponding to an acceleration resolution of 170 ng/?Hz). The IC consumes 6 mW power and measures 0.65 mm2 core area.

Abstract: The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: A capacitor structure including a substrate, a butting conductive layer, a second dielectric layer, a plurality of openings, a bottom electrode layer, a capacitor dielectric layer, a top electrode layer, and a second metal interconnect layer is provided. The substrate has a first dielectric layer and a first metal interconnect layer located in the first dielectric layer in a non-capacitor region. The butting conductive layer is disposed over the first dielectric layer in a capacitor region. The second dielectric layer is disposed over the first dielectric layer and covers the butting conductive layer. The openings include a first opening exposing a portion of the butting conductive layer and a second opening exposing the first metal interconnect layer. The bottom electrode layer, the capacitor dielectric layer, and the top electrode layer are conformally stacked in the first opening sequentially. The second metal interconnect layer is disposed in the openings.

Abstract: A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

Abstract: A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at a first lateral side of the fin and in electrical contact with the conductive region.

Abstract: A DRAM device has a stacked capacitor including a first capacitor section received in a thick insulation film and a second capacitor section overlying the first capacitor section. A portion of the bottom electrode in the second capacitor section has a thickness larger than the thickness of another portion of the bottom electrode in the first capacitor section.

Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.

Abstract: A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.