Abstract: A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element.

Abstract: A semiconductor is provided with: a silicon substrate 2a of a first conductivity type, including a first surface S1a and a second surface S2a; a silicon layer 4a of a second conductivity type, arranged on the first surface S1a of the silicon substrate 2a, including a third surface S3a opposite a junction surface with the silicon substrate 2a; a first electrode 12a arranged on the second surface S2a; a second electrode 14a arranged on the third surface S3a; and an argon added area 6a formed in a semiconductor area formed of the silicon substrate 2a and the silicon layer 4a. The argon added area 6a includes an area indicating an argon concentration of a minimum of 1×1018 cm?3 and a maximum of 2×1020 cm?3.

Abstract: The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (?LHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60 w/cm2).

Abstract: The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (?LHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60 w/cm2).

Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material.

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.