Including Ternary Or Quaternary Compound (epo) Patents (Class 257/E31.022)
  • Patent number: 11749770
    Abstract: A photovoltaic device configured to substantially avoid radiative recombination of photo-generated carriers, reduce loss of energy of the photo-generated carriers through the phonon emission, extract photo-generated carriers substantially exclusively from the multi-frequency satellite valley(s) of the bandstructure of the used semiconductor material as opposed to the single predetermined extremum of the bandstructure. Methodologies of fabrication and operation of such a device.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 5, 2023
    Assignees: Arizona Board of Regents on behalf of Arizona State University, The Board of Regents of the University of Oklahoma
    Inventors: David Ferry, Vincent Whiteside, Ian R. Sellers
  • Patent number: 11581448
    Abstract: An integrated circuit structure comprising a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure wherein a regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operatively coupled with the wafer.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: February 14, 2023
    Assignee: Raytheon Company
    Inventors: Matthew DeJarld, Jeffrey R. LaRoche, Clay T. Long, Lovelace Soirez
  • Patent number: 11551929
    Abstract: This disclosure relates to methods of growing crystalline layers on amorphous substrates by way of an ultra-thin seed layer, methods for preparing the seed layer, and compositions comprising both. In an aspect of the invention, the crystalline layers can be thin films. In a preferred embodiment, these thin films can be free-standing.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: January 10, 2023
    Assignee: THE PENN STATE RESEARCH FOUNDATION
    Inventors: Joshua A. Robinson, Natalie Briggs
  • Patent number: 11536752
    Abstract: High voltage assemblies and detectors are provided. In one aspect, a high voltage assembly includes a high voltage base board and a plurality of sub-detectors. Each sub-detector includes a crystal substrate, a crystal, a high voltage transfer board, and a high voltage cathode board. One of the high voltage transfer board and the high voltage base board includes first and second connection members, and the other one includes first and second contact members. The first connection member is configured to shift relative to the first contact member in response to a first force, and the second connection member is configured to shift relative to the second contact member in response to a second force. A high voltage is applied at both ends of the crystal through electrically contacting the first connection member with the first contact member and electrically contacting the second connection member with the second contact member.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 27, 2022
    Assignee: Neusoft Medical Systems Co., Ltd.
    Inventors: Shuangxue Li, Xin Xiang, Xiaoqing Hu, Songbo Yang
  • Patent number: 11480463
    Abstract: An occupancy sensor covering a wide field in an integrated chip is disclosed. The occupancy sensor includes an array of grating coupled waveguide sensors wherein continuous wave (cw) signals monitor an ambient light field for dynamic changes on times scales of seconds, and high frequency signals map in three-dimensions of the space using time-of-flight (TOF) measurements, pixel level electronics that perform signal processing; array level electronics that perform additional signal processing; and communications and site level electronics that interface with actuators to respond to occupancy sensing.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 25, 2022
    Inventors: Steven R. J. Brueck, Alexander Neumann, Payman Zarkesh-Ha
  • Patent number: 10249514
    Abstract: A semiconductor device includes a semiconductor element, a substrate formed with a recess in a main surface, a conductive layer formed on the substrate and electrically connected to the semiconductor element, and a sealing resin covering the semiconductor element. The substrate is made of an electrically insulative synthetic resin. The recess has a bottom surface on which the semiconductor element is mounted, and an intermediate surface connected to the main surface and the bottom surface. The bottom surface is orthogonal to the thickness direction of the substrate. The intermediate surface is inclined with respect to the bottom surface.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 2, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Yasuhiro Fuwa
  • Patent number: 10128434
    Abstract: The present invention provides a Hall element module for achieving miniaturization. A Hall element module includes a Hall element having an element surface and an element back surface, a terminal portion electrically connected to the Hall element and separated from the Hall element as viewed in a z direction, and a resin package covering at least one portion of each of the Hall element and the terminal. The resin package has a rectangular shape with four sides along the x direction and the y direction as viewed in the z direction. The terminal portion includes a terminal back surface facing the z direction and exposed from the resin package. An end edge of the terminal back surface includes a terminal back surface inclined portion opposed to the Hall element and inclined with respect to the x direction and the y direction as viewed in the z direction.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 13, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Satohiro Kigoshi, Shinsei Mizuta
  • Patent number: 9927499
    Abstract: A semiconductor device includes a semiconductor element, a semiconductor substrate including a substrate main surface and a recess that recedes from the substrate main surface and houses the semiconductor element, a conductive layer electrically connected to the semiconductor element and formed on the semiconductor substrate, a sealing resin covering the semiconductor element and including a resin main surface that faces in the same direction as the substrate main surface, and spherical conductors electrically connected to the conductive layer and protruding outward from the resin main surface.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: March 27, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Mamoru Yamagami
  • Patent number: 8697481
    Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Solar Junction Corporation
    Inventors: Rebecca Elizabeth Jones-Albertus, Pranob Misra, Michael J. Sheldon, Homan B. Yuen, Ting Liu, Daniel Derkacs, Vijit Sabnis, Micahel West Wiemer, Ferran Suarez
  • Patent number: 8680641
    Abstract: An article of manufacture and a method of defining a photodetector element are provided. The article of manufacture includes a photodector element comprising a junction formed by a first III-V semiconductor layer having a first charge type and a second III-V semiconductor layer comprising a second dopant having a second charge type. The second III-V semiconductor layer is disposed between the first III-V semiconductor layer and a wafer. Patterned dopant regions having a third charge type, the third charge type being the same as the first charge type, are disposed in the first III-V semiconductor layer.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: March 25, 2014
    Assignee: University of Iowa Research Foundation
    Inventors: John P. Prineas, Jonathan T. Olesberg, Chris Coretsopoulos
  • Patent number: 8664023
    Abstract: A vapor deposition method of the present invention includes the steps of (i) preparing a mask unit including a shadow mask (81) and a vapor deposition source (85) fixed in position relative to each other, (ii) while moving at least one of the mask unit and the film formation substrate (200) relative to the other, depositing a vapor deposition flow, emitted from the vapor deposition source (85), onto a vapor deposition region (210), and (iii) adjusting the position of a second shutter (111) so that the second shutter (111) blocks a vapor deposition flow traveling toward the vapor deposition unnecessary region (210).
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Shinichi Kawato, Satoshi Inoue, Satoshi Hashimoto
  • Publication number: 20130292685
    Abstract: The present invention relates to optoelectronic device layer structures, light emitting devices, and detectors based upon heterostructures formed between hexagonal boron nitride (hNB) and III-nitrides, and more particularly, to heterojunction devices capable of emitting and detecting photons in the ultraviolet (UV) and extremely ultraviolet (RUV) spectral range. The present invention also relates to neutron detectors based on epitaxially grown hBN thin films (or epitaxial layers) and hBN stacked thin films (or epitaxial layers) to satisfy the thickness required for capturing all incoming neutrons.
    Type: Application
    Filed: May 5, 2012
    Publication date: November 7, 2013
    Applicant: TEXAS TECH UNIVERSITY SYSTEM
    Inventors: Hongxing Jiang, Sashikanth Majety, Rajendra Dahal, Jing Li, Jingyu Lin
  • Patent number: 8575471
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 5, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Publication number: 20130270589
    Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a semiconductor structure; a plurality of contacts on the front side of the semiconductor structure; and a plurality of non-continuous metal contacts on a back side of the semiconductor structure. In an embodiment, a plurality of non-continuous back contacts on an optoelectronic device improve the reflectivity and reduce the losses associated with the back surface of the device.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Applicant: ALTA DEVICES, INC.
    Inventors: Brendan M. KAYES, Sylvia SPRYUTTE, I-Kang DING, Rose TWIST, Gregg HIGASHI
  • Patent number: 8450720
    Abstract: A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 28, 2013
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventors: David Forrai, Darrel Endres, Robert Jones, Michael James Garter
  • Patent number: 8338200
    Abstract: A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: December 25, 2012
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventors: David Forrai, Darrel Endres, Robert Jones, Michael James Garter
  • Publication number: 20120204957
    Abstract: A method for growing an In(x)Al(y)Ga(1?x?y)N layer (where x is greater than zero and less than or equal to one, y is greater than or equal to zero and less than or equal to one and the sum of x and y is less than or equal to one). The method includes supplying plasma-activated nitrogen atoms as a source of nitrogen for the In(x)Al(y)Ga(1?x?y)N layer to a growth surface, where a flux of the plasma-activated nitrogen atoms supplied to the growth surface is at least four times higher than a total flux of aluminium and gallium atoms also supplied to the growth surface, where either the aluminium or gallium flux may or may not be zero; and simultaneously supplying indium atoms and nitrogen-containing molecules to the growth surface.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 16, 2012
    Inventors: David NICHOLLS, Tim Michael Smeeton, Valerie Berryman-Bousquet, Stewart Edward Hooper
  • Patent number: 8242538
    Abstract: A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: August 14, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: Peter Deelman, Ken Elliott, David Chow
  • Publication number: 20120108001
    Abstract: Disclosed are a relatively high-efficiency solar cell and a method for fabricating the same using a micro-heater array. The solar cell may include first and second micro-heaters intersecting each other or being parallel to each other on a substrate, and a plurality of InxGa1-xN p-n junction layers formed using the first and second micro-heaters. The solar cell has improved efficiency because sunlight with various wavelengths may be effectively absorbed by the plurality of InxGa1-xN p-n junction layers. Furthermore, relatively large-sized solar cells may be fabricated, because the plurality of InxGa1-xN p-n junction layers may be formed on a glass substrate using a micro-heater array.
    Type: Application
    Filed: December 29, 2011
    Publication date: May 3, 2012
    Applicants: SAMSUNG SDI CO., LTD., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee CHOI, Jai Yong HAN, Andrei ZOULKARNEEV
  • Patent number: 8129615
    Abstract: The highly mismatched alloy Zn1-yMnyOxTe1-x, 0?y<1 and 0<x<1 and other Group II-IV-Oxygen implanted alloys have been synthesized using the combination of oxygen ion implantation and pulsed laser melting. Incorporation of small quantities of isovalent oxygen leads to the formation of a narrow, oxygen-derived band of extended states located within the band gap of the Zn1-yMnyTe host. With multiple band gaps that fall within the solar energy spectrum, Zn1-yMnyOxTe1-x is a material perfectly satisfying the conditions for single-junction photovoltaics with the potential for power conversion efficiencies surpassing 50%.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: March 6, 2012
    Assignee: The Regents of the University of California
    Inventors: Wladyslaw Walukiewicz, Kin Man Yu, Junqiao Wu
  • Publication number: 20110303268
    Abstract: An InGaAsN solar cell includes an InGaAsN structure having a bandgap between 1.0 eV to 1.05 eV, and a depletion region width of at least 1.0 ?m.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 15, 2011
    Inventors: Wei-Sin TAN, Ian Robert Sellers, Stewart Edward Hooper, Matthias Kauer
  • Publication number: 20110260278
    Abstract: An article of manufacture and a method of defining a photodetector element are provided. The article of manufacture includes a photodector element comprising a junction formed by a first III-V semiconductor layer having a first charge type and a second III-V semiconductor layer comprising a second dopant having a second charge type. The second III-V semiconductor layer is disposed between the first III-V semiconductor layer and a wafer. Patterned dopant regions having a third charge type, the third charge type being the same as the first charge type, are disposed in the first III-V semiconductor layer.
    Type: Application
    Filed: February 18, 2011
    Publication date: October 27, 2011
    Applicant: UNIVERSITY OF IOWA RESEARCH FOUNDATION
    Inventors: John P. PRINEAS, Jonathan T. OLESBERG, Chris CORETSOPOULOS
  • Patent number: 8039369
    Abstract: There is provided a semiconductor light-emitting element and a method of producing the same including high density and high quality quantum dots emitting light at a wavelength of 1.3 ?m. A semiconductor light-emitting element has a first GaAs layer, a second InAs thin film layer having the plurality of InAs quantum dots formed on the first GaAs layer, a third InGaAs layer formed on the second InAs thin film layer having the plurality of InAs quantum dots, and a fourth GaAs layer formed on the third InGaAs layer, wherein the As source is As2.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: October 18, 2011
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Takeru Amano
  • Publication number: 20110232730
    Abstract: An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga1-xInxNyAs1-y-zSbz with a low antimony (Sb) content and with enhanced indium (In) content and enhanced nitrogen (N) content, achieving substantial lattice matching to GaAs and Ge substrates and providing both high short circuit currents and high open circuit voltages in GaInNAsSb subcells for multijunction solar cells. The composition ranges for Ga1-xInxNyAs1-y-zSbz are 0.07?x?0.18, 0.025?y?0.04 and 0.001?z?0.03.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Applicant: Solar Junction Corp.
    Inventors: Rebecca Elizabeth Jones, Homan Bernard Yuen, Ting Liu, Pranob Misra
  • Patent number: 7977141
    Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsubasa Harada, Atsushi Murakoshi
  • Publication number: 20110147707
    Abstract: The present invention provides an image pickup device used to capture an image of an object by receiving light in a near infrared region reflected from the object. The image pickup device includes semiconductor light-receiving elements each having a light-receiving layer with a band gap wavelength of 1.65 to 3.0 ?m.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 23, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi INADA, Yasuhiro IGUCHI, Youichi NAGAI, Hiroki MORI, Kouhei MIURA
  • Publication number: 20110048532
    Abstract: Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. A photovoltaic (PV) unit, according to embodiments of the invention, may have a very thin absorber layer produced by epitaxial lift-off (ELO), all electrical contacts positioned on the back side of the PV device to avoid shadowing, and/or front side and back side light trapping employing a diffuser and a reflector to increase absorption of the photons impinging on the front side of the PV unit. Several PV units may be combined into PV banks, and an array of PV banks may be connected to form a PV module with thin strips of metal or conductive polymer applied at low temperature. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.
    Type: Application
    Filed: November 5, 2010
    Publication date: March 3, 2011
    Applicant: ALTA DEVICES, INC.
    Inventors: Isik C. KIZILYALLI, Melissa ARCHER, Harry ATWATER, Thomas J. GMITTER, Gang HE, Andreas HEGEDUS, Gregg HIGASHI
  • Publication number: 20110048514
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: ANDREW G. NORMAN, Aaron Ptak, William E. McMahon
  • Publication number: 20100301390
    Abstract: An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch.
    Type: Application
    Filed: November 10, 2009
    Publication date: December 2, 2010
    Inventors: Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 7834379
    Abstract: The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 16, 2010
    Assignee: JDS Uniphase Corporation
    Inventors: Zhong Pan, David Venables, Craig Ciesla
  • Patent number: 7776636
    Abstract: A method for reducing dislocation density between an AlGaN layer and a sapphire substrate involving the step of forming a self-organizing porous AlN layer of non-coalescing column-like islands with flat tops on the substrate.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: August 17, 2010
    Assignee: CAO Group, Inc.
    Inventor: Tao Wang
  • Patent number: 7772666
    Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor may be capable of improved thickness uniformity form microlenses formed at a reduced distance from the photodiodes. The CMOS image sensor can include: a semiconductor substrate on which a pixel array is formed, the pixel array including photodiodes formed on the semiconductor substrate to different depths for sensing red, green, and blue signals, respectively; an interlayer dielectric formed on the semiconductor substrate and having a trench at an upper portion of the pixel array; an insulating layer sidewall formed at a side of the trench; and a plurality of microlenses formed on the interlayer dielectric in the trench at predetermined intervals.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: August 10, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heui Gyun Ahn
  • Publication number: 20100155777
    Abstract: In order to increase the spectral response range and improve the mobility of the photo-generated carriers (e.g. in an nBn photodetector), a digital alloy absorber may be employed by embedding one (or fraction thereof) to several monolayers of a semiconductor material (insert layers) periodically into a different host semiconductor material of the absorber layer. The semiconductor material of the insert layer and the host semiconductor materials may have lattice constants that are substantially mismatched. For example, this may performed by periodically embedding monolayers of InSb into an InAsSb host as the absorption region to extend the cutoff wavelength of InAsSb photodetectors, such as InAsSb based nBn devices. The described technique allows for simultaneous control of alloy composition and net strain, which are both key parameters for the photodetector operation.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 24, 2010
    Applicant: California Institute of Technology
    Inventors: Cory J. Hill, David Z. Ting, Sarath D. Gunapala
  • Publication number: 20100126572
    Abstract: Methods and apparatus for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells are provided. A photovoltaic (PV) device generally includes a window layer; an absorber layer disposed below the window layer such that electrons are generated when photons travel through the window layer and are absorbed by the absorber layer; and a plurality of contacts for external connection coupled to the absorber layer, such that all of the contacts for external connection are disposed below the absorber layer and do not block any of the photons from reaching the absorber layer through the window layer. Locating all the contacts on the back side of the PV device avoids solar shadows caused by front side contacts, typically found in conventional solar cells. Therefore, PV devices described herein with back side contacts may allow for increased efficiency when compared to conventional solar cells.
    Type: Application
    Filed: October 23, 2009
    Publication date: May 27, 2010
    Inventors: Isik C. Kizilyalli, Melissa Archer, Harry Atwater, Thomas J. Gmitter, Gang He, Andreas Hegedus, Gregg Higashi
  • Publication number: 20100126570
    Abstract: Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. In one embodiment of a photovoltaic (PV) device, the PV device generally includes an n-doped layer and a p+-doped layer adjacent to the n-doped layer to form a p-n layer such that electric energy is created when electromagnetic radiation is absorbed by the p-n layer. The n-doped layer and the p+-doped layer may compose an absorber layer having a thickness less than 500 nm. Such a thin absorber layer may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.
    Type: Application
    Filed: October 23, 2009
    Publication date: May 27, 2010
    Inventors: Isik C. Kizilyalli, Melissa Archer, Harry Atwater, Thomas J. Gmitter, Gang He, Andreas Hegedus, Gregg Higashi
  • Publication number: 20100095998
    Abstract: A semiconductor structure comprises a first photovoltaic cell comprising a first material, and a second photovoltaic cell comprising a second material and connected in series to the first photovoltaic cell. The conduction band edge of the first material adjacent the second material is at most 0.1 eV higher than a valence band edge of the second material adjacent the material. Preferably, the first material of the first photovoltaic cell comprises ln].?Al?N or lnt_yGayN and the second material of the second photovoltaic cell comprises silicon or germanium. Alternatively, the first material of the first photovoltaic cell comprises InAs or InAsSb and the second material of the second photovoltaic cell comprises GaSb or GaAsSb.
    Type: Application
    Filed: April 9, 2008
    Publication date: April 22, 2010
    Applicant: The Regents of the University of California
    Inventors: Wladyslaw Walukiewicz, Joel W. Ager, III, Kin Man Yu
  • Patent number: 7696593
    Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 13, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Yoshihiro Yoneda, Ryuji Yamabi
  • Patent number: 7659536
    Abstract: According to various embodiments, a photodetector including a first contact layer, a second contact layer, an active region, and a photonic crystal resonant cavity is disclosed. The photonic crystal resonant cavity can operate as a resonant structure to enhance the response of the photodetector at one or more wavelengths. In various embodiments, the photodetectors including a photonic crystal resonant cavity can, for example, demonstrate increased responsivity and quantum efficiency, lower the operating temperature, and/or be used to form a hyperspectral detector.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: February 9, 2010
    Assignee: STC.UNM
    Inventors: Sanjay Krishna, Oskar J. Painter
  • Patent number: 7605406
    Abstract: A rear-illuminated-type photodiode array has (a) a first-electroconductive-type semiconductor substrate, (b) a first-electroconductive-type electrode that is placed at the rear side of the semiconductor substrate and has openings arranged one- or two-dimensionally, (c) an antireflective coating provided at each of the openings of the first-electroconductive-type electrode, (d) a first-electroconductive-type absorption layer formed at the front-face side of the substrate, (e) a leakage-lightwave-absorbing layer that is provided on the absorption layer and has an absorption edge wavelength longer than that of the absorption layer, (f) a plurality of second-electroconductive-type regions that are formed so as to penetrate through the leakage-lightwave-absorbing layer from the top surface and extend into the absorption layer to a certain extent and are arranged one- or two-dimensionally at the positions coinciding with those of the antireflective coatings at the opposite side, and (g) a second-electroconductive-t
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: October 20, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yasuhiro Iguchi
  • Patent number: 7601985
    Abstract: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of AlxGa1?x?yInyN (wherein 0.001?x<0.1, 0<y<1 and x+y<1).
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: October 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshitaka Kinoshita, Hidenori Kamei
  • Publication number: 20090250112
    Abstract: Disclosed are a relatively high-efficiency solar cell and a method for fabricating the same using a micro-heater array. The solar cell may include first and second micro-heaters intersecting each other or being parallel to each other on a substrate, and a plurality of InxGa1-xN p-n junction layers formed using the first and second micro-heaters. The solar cell has improved efficiency because sunlight with various wavelengths may be effectively absorbed by the plurality of InxGa1-xN p-n junction layers. Furthermore, relatively large-sized solar cells may be fabricated, because the plurality of InxGa1-xN p-n junction layers may be formed on a glass substrate using a micro-heater array.
    Type: Application
    Filed: February 9, 2009
    Publication date: October 8, 2009
    Inventors: Junhee Choi, Jai Yong Han, Andrei Zoulkarneev
  • Publication number: 20090250725
    Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.
    Type: Application
    Filed: June 17, 2009
    Publication date: October 8, 2009
    Applicant: HRL LABORATORIES, LLC
    Inventors: Tahir HUSSAIN, Miroslav MICOVIC, Paul HASHIMOTO, Gary PENG, Ara K. KURDOGHLIAN
  • Publication number: 20090140291
    Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 4, 2009
    Inventors: Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
  • Publication number: 20080203425
    Abstract: A phototransistor (400) comprises an emitter (43) comprising antimony, a base (42) comprising antimony, and a collector (41) comprising antimony. Preferably, the emitter, the base and the collector each comprises at least one of AlInGaAsSb, AlGaAsSb, AlGaSb, GaSb and InGaAsSb. The base comprises an emitter-contacting portion (41b) with a base-contacting portion (43a) of the emitter. The collector comprises a base-contacting portion (41b) which is in contact with a collector-contacting portion (421a) of the base. The phototransistor produces an internal gain upon being contacted with light within a receivable wavelength range, preferably greater than 1.7 micrometers. Also, a method of detecting light using such a phototransistor.
    Type: Application
    Filed: January 24, 2005
    Publication date: August 28, 2008
    Inventor: Oleg Sulima
  • Patent number: 7372068
    Abstract: A QWIP structure is disclosed that includes a graded emitter barrier and can further be configured with a blocked superlattice miniband. The graded emitter barrier effectively operates to launch dark electrons into the active quantum well region, thereby improving responsivity. A graded collector barrier may also be included for reverse bias applications. The configuration operates to eliminate or otherwise reduce image artifacts or persistence associated with dielectric relaxation effect in low-background applications.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: May 13, 2008
    Assignee: Bae Systems Information and Electronic Systems Integration Inc.
    Inventors: Mani Sundaram, Axel R Reisinger
  • Publication number: 20080093625
    Abstract: A semiconductor structure includes a GaAs or InP substrate, an InxGa1-xAs epitaxial layer grown on the substrate, where x is greater than about 0.01 and less than about 0.53, and a wider bandgap epitaxial layer grown as a cap layer on top of the InxGa1-xAs epitaxial layer.
    Type: Application
    Filed: December 7, 2005
    Publication date: April 24, 2008
    Inventors: Robert Sacks, Matthew Jazwiecki, Steven Williamson
  • Patent number: 7332751
    Abstract: A rear-illuminated-type photodiode array has (a) a first-electroconductive-type semiconductor substrate, (b) a first-electroconductive-type electrode that is placed at the rear side of the semiconductor substrate and has openings arranged one- or two-dimensionally, (c) an antireflective coating provided at each of the openings of the first-electroconductive-type electrode, (d) a first-electroconductive-type absorption layer formed at the front-face side of the substrate, (e) a leakage-lightwave-absorbing layer that is provided on the absorption layer and has an absorption edge wavelength longer than that of the absorption layer, (f) a plurality of second-electroconductive-type regions that are formed so as to penetrate through the leakage-lightwave-absorbing layer from the top surface and extend into the absorption layer to a certain extent and are arranged one- or two-dimensionally at the positions coinciding with those of the antireflective coatings at the opposite side, and (g) a second-electroconductive-t
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: February 19, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yasuhiro Iguchi
  • Patent number: 7329895
    Abstract: A sensor comprises two photodiodes sensitive to different wavelengths. The photodiodes or detectors are stacked in a vertical relationship to each other. A bandpass filter is provided to limit the wavelengths of light reaching the detectors. The photodiodes are formed of various combinations of materials such as AlGaN or InGaN, or different compositions of the same material. Charge detectors are coupled to each detector to provide a signal representative of the amount of radiation detected in their corresponding bandwidths. A biological sample is provided proximate the filter. A laser is used to illuminate the biological sample to create biofluorescence corresponding to intrinsic tryptophan of bacteria.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: February 12, 2008
    Assignee: Honeywell International Inc.
    Inventors: Barrett E. Cole, Wei Yang, Thomas E. Nohava
  • Patent number: 7307290
    Abstract: A compound semiconductor wafer providing an InGaAs light receiving layer having superior crystal characteristic suitable for a near-infrared sensor includes an InAsxP1-x graded buffer layer consisting of a plurality of layers positioned on an InP substrate and an InAsyP1-y buffer layer positioned on the graded buffer layer, sandwiched between said InP substrate and the InGaAs layer, wherein maximum value of PL light emission intensity at an interface of each of the layers of the graded buffer layer and the buffer layer is, at every interface, smaller than 3/10 of the maximum PL light emission intensity of the buffer layer.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: December 11, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Iwasaki, Shigeru Sawada, Hiroya Kimura, Kenji Ohki
  • Patent number: 7307291
    Abstract: A structure for a gallium-nitride (GaN) based ultraviolet photo detector is provided. The structure contains an n-type contact layer, a light absorption layer, a light penetration layer, and a p-type contact layer, sequentially stacked on a substrate from bottom to top in this order. The layers are all made of aluminum-gallium-indium-nitride (AlGaInN) compound semiconductors. By varying the composition of aluminum, gallium, and indium, the layers, on one hand, can achieve the desired band gaps so that the photo detector is highly responsive to ultraviolet lights having specific wavelengths. On the other hand, the layers have compatible lattice constants so that problems associated with excessive stress are avoided and high-quality epitaxial structure is obtained. The structure further contains a positive electrode, a light penetration contact layer, and an anti-reflective coating layer on top of the p-type contact layer, and a negative electrode on the n-type contact layer.
    Type: Grant
    Filed: January 22, 2005
    Date of Patent: December 11, 2007
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Liang-Wen Wu, Ru-Chin Tu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien