Including Microcrystalline Group Iv Compound (e.g., C-sige, C-sic) (epo) Patents (Class 257/E31.046)
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Patent number: 11966201Abstract: A photovoltaic device includes an electrically-conductive front contact layer; an electrically-conductive back contact layer, the back contact layer being intended to be situated further from a source of incident light than the front contact layer; and a semiconductor-based PIN junction having a substantially amorphous intrinsic silicon layer sandwiched between a P-type doped semiconductor layer and an N-type doped semiconductor layer. The layer of the PIN junction situated closest to the back contact layer is a silicon-germanium alloy layer including at least 2 mol % of germanium.Type: GrantFiled: February 21, 2020Date of Patent: April 23, 2024Assignee: Nivarox-FAR S.A.Inventors: Julien Bailat, Elisa Favre, Jan-Willem Schüttauf
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Patent number: 11496679Abstract: Methods and apparatus for Real-time Satellite Imaging System (10) are disclosed. More particularly, one embodiment of the present invention an imaging sensor (14) on a geostationary satellite having one or more co-collimated telescopes (18). The telescopes (18) illuminate local planes (22) which are sparsely populated with focal plane arrays (24). The focal plane arrays (24) record the entire observable Earth hemisphere at one time, at least once every ten seconds.Type: GrantFiled: February 8, 2021Date of Patent: November 8, 2022Assignee: Live Earth Imaging Enterprises, L.L.C.Inventor: Franklin H. Williams, Jr.
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Patent number: 9029979Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.Type: GrantFiled: November 23, 2012Date of Patent: May 12, 2015Assignee: Hitachi, Ltd.Inventors: Hiroyuki Yoshimoto, Ryuta Tsuchiya, Naoki Tega, Digh Hisamoto, Yasuhiro Shimamoto, Yuki Mori
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Patent number: 8955357Abstract: A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time.Type: GrantFiled: March 13, 2014Date of Patent: February 17, 2015Assignee: Lighting Science Group CorporationInventors: Fredric S. Maxik, David E. Bartine, Theodore Scone, Sepehr Sadeh
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Patent number: 8822315Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.Type: GrantFiled: December 22, 2004Date of Patent: September 2, 2014Assignee: Cree, Inc.Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
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Patent number: 8766236Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.Type: GrantFiled: September 19, 2011Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Tsutomu Tezuka
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Patent number: 8629445Abstract: Provided are a semiconductor device with less leakage current is reduced, a semiconductor device with both of high field effect mobility and low leakage current, an electronic appliance with low power consumption, and a manufacturing method of a semiconductor device in which leakage current can be reduced without an increase in the number of masks. The side surface of a semiconductor layer formed of a semiconductor film having high carrier mobility is not in contact with any of a source electrode and a drain electrode. Further, such a transistor structure is formed without an increase in the number of photomasks and can be applied to an electronic appliance.Type: GrantFiled: February 16, 2012Date of Patent: January 14, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Ryo Tokumaru
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Patent number: 8389995Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.Type: GrantFiled: September 17, 2008Date of Patent: March 5, 2013Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
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Patent number: 8258025Abstract: A microcrystalline semiconductor film with high crystallinity is manufactured. In addition, a thin film transistor with excellent electric characteristics and high reliability, and a display device including the thin film transistor are manufactured with high productivity. A deposition gas containing silicon or germanium is introduced from an electrode including a plurality of projecting portions provided in a treatment chamber of a plasma CVD apparatus, glow discharge is caused by supplying high-frequency power, and thereby crystal particles are formed over a substrate, and a microcrystalline semiconductor film is formed over the crystal particles by a plasma CVD method.Type: GrantFiled: August 2, 2010Date of Patent: September 4, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yukie Suzuki, Yasuyuki Arai, Takayuki Inoue, Erumu Kikuchi
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Patent number: 8101901Abstract: Method and apparatus for acquiring physical information, method for manufacturing semiconductor device including array of a plurality of unit components for detecting physical quantity distribution, light-receiving device and manufacturing method therefor, and solid-state imaging device and manufacturing method therefore are provided. The method for acquiring physical information uses a device for detecting a physical distribution, the device including a detecting part for detecting an electromagnetic wave and a unit signal generating part for generating a corresponding unit signal on the basis of the quantity of the detected electromagnetic wave.Type: GrantFiled: August 28, 2008Date of Patent: January 24, 2012Assignee: Sony CorporationInventor: Atsushi Toda
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Patent number: 8043980Abstract: The invention provides compounds of, and methods for the preparation of compounds of, the molecular formula, SixGeyHz—aXa; wherein X is halogen, and x, y, z, and a are defined herein, and methods for the deposition of high-Ge content Si films on silicon substrates using compounds of the invention.Type: GrantFiled: April 2, 2008Date of Patent: October 25, 2011Assignee: Arizona Board of Regents, A Body Corporate Acting for and on Behalf of Arizona State UniversityInventors: John Kouvetakis, Jesse Tice, Yan-Yan Fang
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Patent number: 7989926Abstract: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure.Type: GrantFiled: September 12, 2006Date of Patent: August 2, 2011Assignee: Showa Denko K.K.Inventor: Takashi Udagawa
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Patent number: 7821033Abstract: A semiconductor component is disclosed herein comprising a drift zone and a drift control zone. The drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. The drift control zone includes at least one first semiconductor layer and one second semiconductor layer. The first semiconductor layer has a higher charge carrier mobility than the second semiconductor layer.Type: GrantFiled: February 15, 2007Date of Patent: October 26, 2010Assignee: Infineon Technologies Austria AGInventors: Stefan Sedlmaier, Anton Mauder, Armin Willmeroth, Franz Hirler
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Patent number: 7495250Abstract: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer is a silicon-germanium layer having a ratio of silicon to germanium of about 50:1 or less, a boron layer formed within the silicon-germanium layer where the boron layer has a full-width half-maximum (FWHM) thickness value of less than 50 nanometers, and a carbon layer formed within the silicon-germanium layer where the carbon layer has an FWHM thickness value of less than 50 nanometers. A ratio of boron to carbon in the etch-stop layer is in a range of about 0.5 to 1.5.Type: GrantFiled: October 26, 2006Date of Patent: February 24, 2009Assignee: Atmel CorporationInventor: Darwin G. Enicks
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Patent number: 7420207Abstract: A photo-detecting device includes a buried doping layer of a first conductivity type and disposed at an upper portion of a silicon substrate. A first silicon epitaxial layer of first conductivity type is disposed on the buried doping layer, and a second silicon epitaxial layer of second conductivity type is disposed on the first silicon epitaxial layer. An isolation doping layer doped of first conductivity type is disposed at a predetermined region of the second silicon epitaxial layer to define a body region of second conductivity type. A silicon germanium epitaxial layer of second conductivity type is disposed on the body region.Type: GrantFiled: December 19, 2005Date of Patent: September 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jin Kim, Kwang-Joon Yoon, Phil-Jae Chang, Kye-Won Maeng, Young-Jun Park
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Publication number: 20070228384Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.Type: ApplicationFiled: January 16, 2007Publication date: October 4, 2007Applicant: STMicroelectronics (Crolles 2) SASInventors: Olivier Kermarec, Yves Campidelli
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Patent number: 7078329Abstract: An insulating film (2) is formed on a semiconductor substrate (1) formed of silicon carbide. A contact hole (3) is formed in the insulating film (2) to expose a part of the upper surface of the semiconductor substrate (1). Then, nickel (Ni) (4?) is formed above the semiconductor substrate (1). Subsequently, the semiconductor substrate (1) is subjected to a heat treatment, whereby the contact portion of nickel (4?) chemically bonds with the semiconductor substrate (1) to become an alloy layer (4) of silicon carbide and nickel. Nickel (4?) on the insulating film (2) is selectively removed by etching liquid for dissolving the nickel.Type: GrantFiled: April 15, 2004Date of Patent: July 18, 2006Assignee: Denso CorporationInventors: Takeshi Endou, Yuuichi Takeuchi