Pin Potential Barrier (epo) Patents (Class 257/E31.061)
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Publication number: 20120178202Abstract: A plasma vapor deposition system for making multi-junction silicon thin film solar cell modules and panels including a flexible substrate disposed about and removably supported by a dual-walled cylindrical substrate support for axially rotating the flexible substrate about its longitudinal axis, the dual-walled cylindrical substrate support comprising an inner wall spaced apart by an outer wall to define a coaxial cavity; a plasma vapor deposition torch located substantially adjacent to the flexible substrate for depositing at least one thin film material layer on an outer surface of the flexible substrate; and a traversing platform for supporting the rotatable substrate support relative to the plasma vapor deposition torch, the rotatable substrate support being traversed along its longitudinal axis by the traversing platform.Type: ApplicationFiled: March 23, 2012Publication date: July 12, 2012Inventor: Mohd Aslami
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Publication number: 20120164781Abstract: A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible.Type: ApplicationFiled: March 1, 2012Publication date: June 28, 2012Applicant: Palo Alto Research Center IncorporatedInventors: Robert A. Street, William S. Wong
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Patent number: 8193601Abstract: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.Type: GrantFiled: January 22, 2010Date of Patent: June 5, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, William S. Wong, Rene A. Lujan, Scott J. Limb
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Patent number: 8178382Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.Type: GrantFiled: January 13, 2011Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurri A. Vlasov, Ying Zhang
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Publication number: 20120086007Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.Type: ApplicationFiled: December 15, 2011Publication date: April 12, 2012Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
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Patent number: 8154096Abstract: An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.Type: GrantFiled: July 12, 2010Date of Patent: April 10, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Shinya Hasegawa, Hidekazu Takahashi, Tatsuya Arao
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Publication number: 20120080081Abstract: A method of manufacturing a layer stack adapted for a thin-film solar cell is and a precursor for a solar cell are described. The method includes depositing a TCO layer over a transparent substrate, depositing a first conductive-type layer a first p-i-n junction configured for the solar cell, depositing a first intrinsic-type layer of a first p-i-n junction configured for the solar cell and depositing a further conductive-layer with a conductivity opposite to the first conductive-type layer first p-i-n junction configured for the solar cell. The method further includes providing for a SiOx-containing intermediate layer by chemical vapor deposition and depositing a second p-i-n junction configured for the solar cell, wherein the SiOx-containing intermediate layer is provided within the a further conductive-type layer, and wherein the SiOx-containing layer has a thickness of 17 nm or less.Type: ApplicationFiled: October 12, 2010Publication date: April 5, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Stefan KLEIN, Tobias STOLLEY, Susanne Buschbaum, Martin Rohde, Konrad Schwanitz, Christian Stoemmer
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Publication number: 20120067409Abstract: Disclosed is a method for manufacturing a photovoltaic device that includes: providing a substrate having a first electrode formed thereon; forming a first unit cell, the first unit cell including a first conductive silicon layer, an intrinsic silicon layer and a second conductive silicon layer, which are sequentially stacked from the first electrode; exposing to the air either a portion of an intermediate reflector formed on the first unit cell or the second conductive silicon layer of the first unit cell; forming the rest of the intermediate reflector or the entire intermediate reflector on the second conductive silicon layer of the first unit cell in a second manufacturing system; and forming a second unit cell on the intermediate reflector in the second manufacturing system, the second unit cell including a first conductive silicon layer, an intrinsic silicon layer and a second conductive silicon layer, sequentially stacked.Type: ApplicationFiled: March 21, 2011Publication date: March 22, 2012Inventor: Seung-Yeop Myong
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PHOTOVOLTAIC DEVICE INCLUDING FLEXIBLE OR INFLEXIBLE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
Publication number: 20120060906Abstract: Disclosed is a method for manufacturing a photovoltaic device including a substrate; a first electrode and a second electrode which are placed over the substrate; a first conductive semiconductor layer, an intrinsic semiconductor layer including a first sub-layer and a second sub-layer, and a second conductive semiconductor layer, which are placed between the first electrode and the second electrode. The method comprising: forming the first sub-layer having a first crystal volume fraction in an ‘i’-th process chamber group (‘i’ is a natural number equal to or greater than 1) among a plurality of process chamber groups; and forming the second sub-layer in an ‘i+1’-th process chamber group among the plurality of the process chamber groups, the second sub-layer contacting with the first sub-layer, including crystalline silicon grains and having a second crystal volume fraction greater than the first crystal volume fraction.Type: ApplicationFiled: March 15, 2011Publication date: March 15, 2012Inventor: Seung-Yeop Myong -
Publication number: 20120038018Abstract: A photoelectric conversion element includes a first semiconductor layer that exhibits a first conductivity type and is provided in a selective area over a substrate, a second semiconductor layer that exhibits a second conductivity type and is disposed opposed to the first semiconductor layer, and a third semiconductor layer that is provided between the first and second semiconductor layers and exhibits a substantially intrinsic conductivity type. The third semiconductor layer has at least one corner part that is not in contact with the first semiconductor layer.Type: ApplicationFiled: August 2, 2011Publication date: February 16, 2012Applicant: SONY CORPORATIONInventors: Yasuhiro Yamada, Tsutomu Tanaka, Makoto Takatoku, Ryoichi Ito
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Publication number: 20120034731Abstract: A photoelectric conversion device manufacturing system in which a photoelectric conversion device is manufactured, the photoelectric conversion device including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer which are sequentially layered on a transparent-electroconductive film formed on a substrate in the photoelectric conversion device.Type: ApplicationFiled: April 6, 2010Publication date: February 9, 2012Applicant: ULVAC, INC.Inventors: Takafumi Noguchi, Hideyuki Ogata, Katsuhiko Mori, Yasuo Shimizu, Hiroto Uchida, Shin Asari
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Patent number: 8110887Abstract: Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate (20) including a transparency base substrate (2), a plurality of active elements and a photodetector. The photodetector includes a light-shielding layer (3) provided on the base substrate (2), and a photodiode (1) arranged on an upper layer of the light-shielding layer (3). The light-shielding layer (3) is overlapped with the photodiode (1) in the thickness direction of the base substrate (2). The photodiode (1) includes a silicon layer (11) insulated electrically from the light-shielding layer (3). The silicon layer (11) includes a p-layer (11c), an i-layer (11b) and an n-layer (11a) that are provided adjacent to each other in the planar direction. The p-layer (11c) is formed so that its area (length Lp) will be larger than the area (length Ln) of the n-layer (11a).Type: GrantFiled: June 12, 2008Date of Patent: February 7, 2012Assignee: Sharp Kabushiki KaishaInventors: Christopher Brown, Hiromi Katoh
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Patent number: 8101971Abstract: Novel structures of the photodetector having broad spectral ranges detection capability are provided. The photodetector offers high quantum efficiency>95% over wide spectral ranges, high frequency response>10 GHz (@3 dB). The photodiode array of N×N (or M×N) elements is also provided. The array also offers wide spectral detection ranges ultraviolet to 2500 nm with high quantum efficiency>95% and high frequency response of >10 GHz, cross-talk of <0.1%. In the array, each photodiode is independently addressable and is made either as top-illuminated or as bottom illuminated type detector. The photodiode and its array provided in this invention, could be used in multiple purpose applications such as telecommunication, imaging, and sensing applications including surveillance, satellite tracking, advanced lidar systems, etc. The advantages of this photodetectors are that they are uncooled and performance will not be degraded under wide range of temperature variation.Type: GrantFiled: April 7, 2009Date of Patent: January 24, 2012Assignee: Banpil Photonics, Inc.Inventor: Achyut Kumar Dutta
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Publication number: 20110315861Abstract: It is an object to provide a photoelectric conversion device whose power consumption and a mounting area are reduced and yield is improved and further to provide a photoelectric conversion device whose number of manufacturing processes and manufacturing cost are reduced. A photoelectric conversion device includes a photoelectric conversion element for outputting photocurrent corresponding to illuminance, and a resistor changing resistance corresponding to illuminance. In the photoelectric conversion device, one terminal of the photoelectric conversion element and one terminal of the resistor are electrically connected in series; the other terminal of the photoelectric conversion element is connected to a high power supply potential; the other terminal of the resistor is connected to a low power supply potential; and a light intensity adjusting unit is provided on a light reception surface side of the photoelectric conversion element or the resistor to adjust illuminance.Type: ApplicationFiled: June 17, 2011Publication date: December 29, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yukinori SHIMA, Atsushi HIROSE
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Publication number: 20110315988Abstract: Described herein is a device comprising: a substrate; one or more of a nanostructure extending essentially perpendicularly from the substrate; wherein the nanostructure comprises a core of a doped semiconductor, an first layer disposed on the core, and a second layer of an opposite type from the core and disposed on the first layer.Type: ApplicationFiled: May 12, 2011Publication date: December 29, 2011Applicant: ZENA TECHNOLOGIES, INC.Inventors: Young-June Yu, Munib Wober
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Publication number: 20110316427Abstract: A photodiode (10) according to the present invention is provided with a p-type semiconductor region (11), an i-type semiconductor region (12) and an n-type semiconductor region (13). A protection film (9) provided on the surface of the photodiode has been removed from at least a light receiving portion of the photodiode (10). Accordingly, the present invention provides the photodiode (10) that has less changes in its characteristics even with the prolonged use and a display device that uses the photodiode (10).Type: ApplicationFiled: February 3, 2010Publication date: December 29, 2011Applicant: SHARP KABUSHIKI KAISHAInventor: Nami Okajima
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Publication number: 20110309410Abstract: A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.Type: ApplicationFiled: June 24, 2011Publication date: December 22, 2011Inventor: Shimon Maimon
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Publication number: 20110308585Abstract: A dual transparent conductive material layer is provided between a p-doped semiconductor layer and a substrate layer of a photovoltaic device. The dual transparent conductive material layer includes a first transparent conductive material and a second transparent conductive material wherein the second transparent conductive material is nano-structured. The nano-structured second transparent conductive material acts as a protective layer for the underlying first transparent conductive material. The nano-structured transparent conductive material provides a benefit of a higher Eg of the underlying first transparent conductive material surface and a very high resilience to hydrogen plasma from the nano-structures during the formation of the p-doped semiconductor layer.Type: ApplicationFiled: June 16, 2010Publication date: December 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pratik P. Joshi, Young-Hee Kim, Steven E. Steen
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Publication number: 20110309240Abstract: Described herein is a device operable to detect polarized light comprising: a substrate; a first subpixel; a second subpixel adjacent to the first subpixel; a first plurality of features in the first subpixel and a second plurality of features in the second subpixel, wherein the first plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a first direction parallel to the substrate and the second plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a second direction parallel to the substrate; wherein the first direction and the second direction are different; the first plurality of features and the second plurality of features react differently to the polarized light.Type: ApplicationFiled: March 14, 2011Publication date: December 22, 2011Applicant: ZENA TECHNOLOGIES, INC.Inventors: Young-June YU, Munib Wober
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Publication number: 20110309331Abstract: Described herein is device configured to be a solar-blind UV detector comprising a substrate; a plurality of pixels; a plurality of nanowires in each of the plurality of pixel, wherein the plurality of nanowires extend essentially perpendicularly from the substrate.Type: ApplicationFiled: March 15, 2011Publication date: December 22, 2011Applicant: ZENA TECHNOLOGIES, INC.Inventors: Young-June Yu, Munib WOBER
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Publication number: 20110266598Abstract: In a rear surface incidence type CMOS image sensor having a wiring layer 720 on a first surface (front surface) of an epitaxial substrate 710 in which a photodiode, a reading circuit (an n-type region 750 and an n+ type region 760) and the like are disposed, and a light receiving plane in a second surface (rear surface), the photodiode and a P-type well region 740 on the periphery of the photodiode are disposed in a layer structure that does not reach the rear surface (light receiving surface) of the substrate, and an electric field is formed within the substrate 710 to properly lead electrons entering from the rear surface (light receiving surface) of the substrate to the photodiode. The electric field is realized by providing a concentration gradient in a direction of depth of the epitaxial substrate 710. Alternatively, the electric field can be realized by providing a rear-surface electrode 810 or 840 for sending a current.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: Sony CorporationInventor: Keiji Mabuchi
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Publication number: 20110259407Abstract: Disclosed is a method of fabricating a microlens. The method includes forming a self assembly monolayer having a strong hydrophobicity on a substrate; forming a plurality of ink droplets on the self assembly monolayer by jetting a transparent ink using an inkjet apparatus, the transparent ink including a first solvent having a first boiling point, a second solvent having a second boiling point lower than the first boiling point and a silicon oxide (SiOx) solid material dispersed in the first and second solvents; and drying the plurality of ink droplets.Type: ApplicationFiled: April 20, 2011Publication date: October 27, 2011Inventors: Jae-Hyun KIM, Seong-Kee Park, Jung-shik Lim, Tae-Young Lee, Min-Cheol Kim
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Publication number: 20110253203Abstract: Disclosed is a photovoltaic device that comprises: a first electrode including a transparent conductive oxide layer; a first unit cell being placed on the first electrode; a second unit cell being placed on the first unit cell; and a second electrode being placed on the second unit cell, wherein the intrinsic semiconductor layer of the first unit cell includes hydrogenated amorphous silicon or hydrogenated amorphous silicon based material, wherein an intrinsic semiconductor layer of the second unit cell includes hydrogenated microcrystalline silicon or hydrogenated microcrystalline silicon based material, and wherein a ratio of a root mean square roughness to an average pitch of a texturing structure formed on the surface of the first electrode is equal to or more than 0.05 and equal to or less than 0.13.Type: ApplicationFiled: January 9, 2011Publication date: October 20, 2011Inventor: Seung-Yeop MYONG
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Publication number: 20110248316Abstract: A semiconductor-based SWIR infrared detector sensitive to wavelengths shorter than about 2.5 microns comprises a stack of semiconductor layers based on III-V materials forming a PIN photodiode. The stack includes a naked electrical contact, called a lower electrical contact, serving as an optical window; and a detection layer sensitive to said wavelengths. The lower contact comprises at least one layer of indirect-bandgap III-V material(s) doped n-type, pseudomorphic or lattice matched with a substrate intended to serve as a temporary substrate possibly being made of a III-V material such as InP or GaAs or of silicon or germanium.Type: ApplicationFiled: December 8, 2009Publication date: October 13, 2011Applicant: THALESInventors: Philippe Bois, Olivier Parillaud, Xavier Marcadet, Michel Papuchon
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Patent number: 8035184Abstract: This invention relates to imaging device and its related transferring technologies to independent substrate able to attain significant broadband capability covering the wavelengths from ultra-violet (UV) to long-Infrared. More particularly, this invention is related to the broadband image sensor (along with its manufacturing technologies), which can detect the light wavelengths ranges from as low as UV to the wavelengths as high as 20 ?m covering the most of the wavelengths using of the single monolithic image sensor on the single wafer. This invention is also related to the integrated circuit and the bonding technologies of the image sensor to standard integrated circuit for multicolor imaging, sensing, and advanced communication. Our innovative approach utilizes surface structure having more than micro-nano-scaled 3-dimensional (3-D) blocks which can provide broad spectral response.Type: GrantFiled: September 25, 2009Date of Patent: October 11, 2011Assignee: Banpil Photonics, Inc.Inventors: Achyut Kumar Dutta, Robert Olah
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Patent number: 8030727Abstract: An image sensor includes a semiconductor substrate, an interconnection and an interlayer dielectric, an image sensing device, a trench, a buffer layer, a barrier pattern, a via hole, and a metal contact. The semiconductor substrate includes a readout circuitry. The interconnection and an interlayer dielectric layer are formed on and/or over the semiconductor substrate while the interconnection is connected to the readout circuitry. The image sensing device may be formed on and/or over the interlayer dielectric and a trench may be formed in the image sensing device, the trench corresponding to the interconnection. The buffer layer may be formed on a sidewall of the trench. The barrier pattern may be formed on the buffer layer with the via hole penetrating through the image sensing device and the interlayer dielectric under the barrier pattern and exposing the interconnection. The metal contact may be formed in the via hole.Type: GrantFiled: December 21, 2009Date of Patent: October 4, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki-Jun Yun
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Patent number: 8022494Abstract: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to form a p-n junction. In addition, a barrier layer, for preventing movement of carriers from the substrate toward the active region, is provided on the side of the active regions toward the substrate.Type: GrantFiled: January 31, 2007Date of Patent: September 20, 2011Assignees: FUJIFILM Corporation, Massachusetts Institute of TechnologyInventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
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Patent number: 8022495Abstract: A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, and a first type window layer disposed over the intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer is disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.Type: GrantFiled: April 8, 2009Date of Patent: September 20, 2011Assignee: Emcore CorporationInventors: Xiang Gao, Alex Ceruzzi, Linlin Liu, Stephen Schwed
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Publication number: 20110221026Abstract: Disclosed is a photovoltaic device. The photovoltaic device of the present invention includes: a first electrode and a second electrode, which are sequentially placed on a substrate; a first photoelectric conversion layer being placed between the first electrode and the second electrode, and including an n-type semiconductor layer, an intrinsic semiconductor layer and a p-type semiconductor layer, which are sequentially stacked; a second photoelectric conversion layer being placed between the first photoelectric conversion layer and the second electrode, and including an n-type semiconductor layer, an intrinsic semiconductor layer and a p-type semiconductor layer, which are sequentially stacked; and light transmitting particles placed within the second electrode.Type: ApplicationFiled: March 15, 2011Publication date: September 15, 2011Inventor: Seung-Yeop Myong
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Publication number: 20110204466Abstract: A photoelectric conversion device manufacturing method, includes: continuously forming a first p-type semiconductor layer, a first i-type semiconductor layer, and a first n-type semiconductor layer, which constitute a first-photoelectric conversion unit, and a second p-type semiconductor layer which constitutes a second-photoelectric conversion unit, in decompression chambers that are different from each other; exposing the second p-type semiconductor layer to an air atmosphere; and forming a second i-type semiconductor layer and a second n-type semiconductor layer, which constitute the second-photoelectric conversion unit, on the second p-type semiconductor layer of the second-photoelectric conversion unit which was exposed to the air atmosphere, in the same decompression chamber.Type: ApplicationFiled: August 28, 2009Publication date: August 25, 2011Applicant: ULVAC, INC.Inventors: Shinichi Asahina, Hirota Uchida, Shin Asari, Masanori Hashimoto, Tetsushi Fujinaga, Tadamasa Kobayashi, Masafumi Wakai, Kenichi Imakita, Yoshinobu Ue, Kazuya Saito, Kyuzo Nakamura
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Patent number: 8004012Abstract: A photo-detector with a reduced G-R noise comprises two n-type narrow bandgap layers surrounding a middle barrier layer having an energy bandgap at least equal to the sum of the bandgaps of the two narrow bandgap layers. Under the flat band conditions the conduction band edge of each narrow bandgap layer lies below the conduction band edge of the barrier layer by at least the bandgap energy of the other narrow bandgap layer. When biased with an externally applied voltage, the more negatively biased narrow bandgap layer is the contact layer and the more positively biased narrow bandgap layer is the photon absorbing layer.Type: GrantFiled: March 29, 2007Date of Patent: August 23, 2011Assignee: Semi-Conductor Devices—An Elbit Systems-Rafael PartnershipInventor: Philip Klipstein
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Patent number: 7993956Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.Type: GrantFiled: December 29, 2006Date of Patent: August 9, 2011Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
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Patent number: 7986022Abstract: A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.Type: GrantFiled: November 19, 2009Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Toshiharu Furukawa, Robert R. Robison, William R. Tonti, Richard Q. Williams
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Publication number: 20110168256Abstract: A photonic device, a method of making the device and a nano-scale antireflector employ a bramble of nanowires. The photonic device and the method include a first layer of a microcrystalline material provided on a substrate surface and a second layer of a microcrystalline material provided on the substrate surface horizontally spaced from the first layer by a gap. The photonic device and the method further include, and the nano-scale antireflector includes, the bramble of nanowires formed between the first layer and the second layer. The nanowires have first ends integral to crystallites in each of the first layer and the second layer. The nanowires of the bramble extend into the gap from each of the first layer and the second layer.Type: ApplicationFiled: October 3, 2008Publication date: July 14, 2011Inventors: Shih-Yuan Wang, R. Stanley Williams, Nobuhiko Kabayashi
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METHOD FOR MANUFACTURING THIN FILM TYPE SOLAR CELL, AND THIN FILM TYPE SOLAR CELL MADE BY THE METHOD
Publication number: 20110162684Abstract: A method for manufacturing a thin film type solar cell and a thin film type solar cell manufactured by the method is disclosed. The method is comprised of a first process for forming a plurality of unit front electrode patterns at predetermined intervals on a substrate; a second process for forming a semiconductor layer pattern on the substrate, wherein the semiconductor layer pattern is comprised of a separating part to divide the solar cell into unit cells, and a contact part to connect the electrode patterns electrically; and a third process for forming a plurality of unit rear electrode patterns which are respectively connected with the unit front electrode patterns through the contact part, and are separated from one another by the separating part.Type: ApplicationFiled: August 6, 2008Publication date: July 7, 2011Applicant: JUSUNG ENGINEERING CO., LTD.Inventors: Jae Ho Kim, Jin Hong, Chang-Sil Yang -
Publication number: 20110155229Abstract: A solar cell and a manufacturing method thereof have been disclosed in the present invention. According to the present invention, the p-layer or n-layer with the grooves helps to strengthen the electric filed of the solar cell and facilitates the carrier collection, thereby improving the overall efficiency of the solar cell.Type: ApplicationFiled: December 29, 2010Publication date: June 30, 2011Inventors: King Wai Lam, Wa-Sze Tsang
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Publication number: 20110147874Abstract: Consistent with the present disclosure, a current blocking layer is provided between output waveguides carrying light to be sensed by the photodiodes in a balanced photodetector, and the photodiodes themselves. Preferably, the photodiodes are provided above the waveguides and sense light through evanescently coupling with the waveguides. In addition, the current blocking layer may include alternating p and n-type conductivity layers, such that, between adjacent ones of such layers, a reverse biased pn-junction is formed. The pn-junctions, therefore, limit the amount of current flowing from one photodiode of the balanced detector to the other, thereby improving performance.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: RADHAKRISHNAN L. NAGARAJAN, ANDREW G. DENTAI, SCOTT CORZINE, STEVEN NGUYEN, VIKRANT LAL, Jacco L. Pleumeekers, Peter W. Evans
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Publication number: 20110147878Abstract: An optical detector includes a detector surface operable to receive light, a depleted field region coupled to the underside of the detector surface, a charge collection node underlying the depleted field region, an active pixel area that includes the portion of the depleted field region above the charge collection node and below the detector surface, and two or more guard regions coupled to the underside of the detector surface and outside of the active pixel area. The depleted field region includes an intrinsic or a near-intrinsic material. The charge collection node has a first width, and the guard regions are separated by a second width that is greater than the first width of the charge collection node. The guard regions are operable to prevent crosstalk to an adjacent optical detector.Type: ApplicationFiled: November 3, 2009Publication date: June 23, 2011Applicant: Raytheon CompanyInventors: John L. Vampola, Sean P. Kilcoyne, Robert E. Mills, Kenton T. Veeder
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Publication number: 20110121424Abstract: Radiation-absorbing semiconductor devices and associated methods of making and using are provided. In one aspect, for example, a method for making a radiation-absorbing semiconductor device having enhanced photoresponse can include forming an active region on a surface of a low oxygen content semiconductor, and annealing the low oxygen content semiconductor to a temperature of from about 300° C. to about 1100° C., wherein the forming of the active region and the annealing of the low oxygen content semiconductor are performed in a substantially oxygen-depleted environment.Type: ApplicationFiled: April 30, 2010Publication date: May 26, 2011Inventors: James Carey, Xia Li, Susan Alie, Martin U. Pralle
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Patent number: 7948006Abstract: A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.Type: GrantFiled: June 1, 2009Date of Patent: May 24, 2011Assignee: JDS Uniphase CorporationInventors: Zhong Pan, David Venables
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Publication number: 20110111551Abstract: Provided is a photoelectric conversion device fabrication method that realizes both high productivity and high conversion efficiency by rapidly forming an n-layer having good coverage. The fabrication method for a photoelectric conversion device includes a step of forming a silicon photoelectric conversion layer on a substrate by a plasma CVD method. In the fabrication method for the photoelectric conversion device, the step of forming the photoelectric conversion layer includes a step of forming an i-layer formed of crystalline silicon and a step of forming, on the i-layer, an n-layer under a condition with a hydrogen dilution ratio of 0 to 10, inclusive.Type: ApplicationFiled: August 18, 2009Publication date: May 12, 2011Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kengo Yamaguchi, Satoshi Sakai, Yoshiaki Takeuchi
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Publication number: 20110100444Abstract: A photovoltaic device that exhibits increased open-circuit voltage and an improved fill factor due to an improvement in the contact properties between the n-layer and a back-side transparent electrode layer or intermediate contact layer, and a process for producing the photovoltaic device. The photovoltaic device comprises a photovoltaic layer having a p-layer, an i-layer and an n-layer stacked on top of a substrate, wherein the n-layer comprises a nitrogen-containing n-layer and an interface treatment layer formed on the opposite surface of the nitrogen-containing n-layer to the substrate, the nitrogen-containing n-layer comprises nitrogen atoms at an atomic concentration of not less than 1% and not more than 20%, and has a crystallization ratio of not less than 0 but less than 3, and the interface treatment layer has a crystallization ratio of not less than 1 and not more than 6.Type: ApplicationFiled: July 8, 2009Publication date: May 5, 2011Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Shigenori Tsuruga, Kengo Yamaguchi, Saneyuki Goya, Satoshi Sakai
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Publication number: 20110092012Abstract: A process for producing a photovoltaic device, wherein when providing an n-type amorphous silicon layer on an i-type amorphous silicon layer, a desired crystallization ratio can be achieved without reducing the deposition rate.Type: ApplicationFiled: October 30, 2008Publication date: April 21, 2011Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Hiroshi Mashima, Koichi Asakusa, Akemi Takano, Nobuki Yamashita, Yoshiaki Takeuchi
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Patent number: 7928529Abstract: A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made of tantalum or a tantalum compound) is formed on the surface of the multilayer wiring area to attenuate incident light on circuit element area.Type: GrantFiled: April 9, 2009Date of Patent: April 19, 2011Assignee: Texas Instruments IncorporatedInventor: Hiroyuki Tomomatsu
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Patent number: 7919398Abstract: Embodiments of the invention as recited in the claims relate to thin film multi-junction solar cells and methods and apparatuses for forming the same. In one embodiment a method of forming a thin film multi-junction solar cell over a substrate is provided. The method comprises positioning a substrate in a reaction zone, providing a gas mixture to the reaction zone, wherein the gas mixture comprises a silicon containing compound and hydrogen gas, forming a first region of an intrinsic type microcrystalline silicon layer on the substrate at a first deposition rate, forming a second region of the intrinsic type microcrystalline silicon layer on the substrate at a second deposition rate higher than the first deposition rate, and forming a third region of the intrinsic type microcrystalline silicon layer on the substrate at a third deposition rate lower than the second deposition rate.Type: GrantFiled: June 26, 2009Date of Patent: April 5, 2011Assignee: Applied Materials, Inc.Inventors: Yong Kee Chae, Soo Young Choi, Shuran Sheng
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Publication number: 20110073979Abstract: The present invention provides a detection element that can suppress leak current from an end face of a semiconductor layer. That is, of an n+ layer and a p+ layer respectively disposed between an i layer, in which an electric charge is generated as a result of being illuminated with light, and a pair of electrodes, an edge portion of a formed face of the p+ layer is formed further inward than that of the i layer.Type: ApplicationFiled: September 21, 2010Publication date: March 31, 2011Applicant: FUJIFILM CORPORATIONInventor: Yoshihiro OKADA
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Patent number: 7915612Abstract: A photoelectric conversion device includes a p-type layer, an i-type layer and an n-type layer each made of a silicon base semiconductor, stacked in this order, wherein the i-type layer contains n-type impurities in a concentration of 1.0×1016 to 2.0×1017 cm?3.Type: GrantFiled: January 7, 2008Date of Patent: March 29, 2011Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Nasuno, Yasuaki Ishikawa, Takanori Nakano
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Publication number: 20110057129Abstract: Various embodiments of a package-on-package optical sensor comprising three distinct different packages are disclosed. The three different packages are combined to form the optical proximity sensor, where the first package is a light emitter package, the second package is a light detector package, and the third package is an integrated circuit package. First and second infrared light pass components are molded or casted atop the light emitter package and the light detector package after they have been mounted atop the integrated circuit package. An infrared light cut component is then molded or casted between and over portions of the light emitter package and the light detector package.Type: ApplicationFiled: September 10, 2009Publication date: March 10, 2011Applicant: Avago Technologies ECBU (Singapore) Pte. Ltd.Inventors: Yufeng Yao, Chi Boon Ong
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Patent number: 7902620Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.Type: GrantFiled: August 14, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurii A. Vlasov, Ying Zhang
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Publication number: 20110048518Abstract: Inorganic solar cells having a nano-patterned p-n or p-i-n junction to reduce electron and hole travel distance to the separation interface to be less than the magnitude of the drift length or diffusion length, and meanwhile to maintain adequate active material to absorb photons. Formation of the inorganic solar cells may include one or more nano-lithography steps.Type: ApplicationFiled: August 17, 2010Publication date: March 3, 2011Applicants: MOLECULAR IMPRINTS, INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Shuqiang Yang, Sidlgata V. Sreenivasan, Frank Y. Xu