Pin Potential Barrier (epo) Patents (Class 257/E31.061)
  • Publication number: 20080179700
    Abstract: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to form a p-n junction. In addition, a barrier layer, for preventing movement of carriers from the substrate toward the active region, is provided on the side of the active regions toward the substrate.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Applicants: FUJIFILM Corporation, Massachusetts Institute of Technology
    Inventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
  • Patent number: 7368750
    Abstract: A semiconductor light-receiving device includes: a semi-insulating substrate; a semiconductor layer of a first conduction type that is formed on the semi-insulating substrate; a buffer layer of the first conduction type that is formed on the semi-insulating substrate and has a lower impurity concentration than the semiconductor layer of the first conduction type; a light absorption layer that is formed on the buffer layer and generates carriers in accordance with incident light; a semiconductor layer of a second conduction type that is formed on the light absorption layer; and a semiconductor intermediate layer that is interposed between the buffer layer and the light absorption layer, and has a forbidden bandwidth within a range lying between the forbidden bandwidth of the buffer layer and the forbidden bandwidth of the light absorption layer.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: May 6, 2008
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Gang Wang, Yoshihiro Yoneda
  • Publication number: 20080099870
    Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.
    Type: Application
    Filed: August 10, 2007
    Publication date: May 1, 2008
    Applicant: ICEMOS TECHNOLOGY CORPORATION
    Inventors: Robin Wilson, Conor Brogan, Hugh Griffin, Cormac MacNamara
  • Patent number: 7352044
    Abstract: A solar battery 10 comprises a metal electrode layer 12, a pin junction 100, and a transparent electrode layer 16 which are successively laminated on a substrate 11 such as a silicon substrate. The pin junction 100 comprises an n-layer 13, an i-layer 14, and a p-layer 15 which are laminated in succession. The i-layer 14 is formed by amorphous iron silicide (FexSiy:H) containing hydrogen atoms. In the i-layer 14, at least a part of the hydrogen atoms contained therein terminate dangling bonds of silicon atoms and/or iron atoms, so that a number of trap levels which may occur in an amorphous iron silicide film can be eliminated, whereby the i-layer 14 exhibits a characteristic as an intrinsic semiconductor layer.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: April 1, 2008
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroshi Yamada, Hisao Morooka, Kazuo Nishi
  • Patent number: 7329895
    Abstract: A sensor comprises two photodiodes sensitive to different wavelengths. The photodiodes or detectors are stacked in a vertical relationship to each other. A bandpass filter is provided to limit the wavelengths of light reaching the detectors. The photodiodes are formed of various combinations of materials such as AlGaN or InGaN, or different compositions of the same material. Charge detectors are coupled to each detector to provide a signal representative of the amount of radiation detected in their corresponding bandwidths. A biological sample is provided proximate the filter. A laser is used to illuminate the biological sample to create biofluorescence corresponding to intrinsic tryptophan of bacteria.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: February 12, 2008
    Assignee: Honeywell International Inc.
    Inventors: Barrett E. Cole, Wei Yang, Thomas E. Nohava
  • Publication number: 20080006895
    Abstract: In a mesa type PIN-PD formed using a heavily doped semiconductor material, a high frequency response is degraded as slow carriers occur in a heavily doped layer when light incident into a light receiving section transmits through an absorbing layer and reaches the heavily doped layer on a side near the substrate. In a p-i-n multilayer structure, a portion corresponding to a light receiving section of a heavily doped layer on a side near a substrate is previously made thinner than the periphery of the light receiving section by an etching or selective growth technique, over which an absorbing layer and another heavily doped layer are grown to form the light receiving section of mesa structure. This makes it possible to form a good ohmic contact and to realize a PIN-PD with excellent high frequency response characteristics.
    Type: Application
    Filed: February 5, 2007
    Publication date: January 10, 2008
    Inventors: Kazuhiro Komatsu, Yasushi Sakuma, Daisuke Nakai, Kaoru Okamoto, Ryu Washino
  • Publication number: 20070278606
    Abstract: An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.
    Type: Application
    Filed: April 19, 2007
    Publication date: December 6, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya SASAGAWA, Shinya HASEGAWA, Hidekazu TAKAHASHI, Tatsuya ARAO
  • Publication number: 20070272996
    Abstract: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
    Type: Application
    Filed: April 13, 2007
    Publication date: November 29, 2007
    Applicant: Applied Materials, Inc.
    Inventors: Francisco Leon, Lawrence West
  • Publication number: 20070138588
    Abstract: A backlit photodiode array includes a semiconductor substrate having first and second main surfaces opposite to each other. A first dielectric layer is formed on the first main surface. First and second conductive vias are formed extending from the second main surface through the semiconductor substrate and the first dielectric layer. The first and second conductive vias are isolated from the semiconductor substrate by a second dielectric material. A first anode/cathode layer of a first conductivity is formed on the first dielectric layer and is electrically coupled to the first conductive via. An intrinsic semiconductor layer is formed on the first anode/cathode layer. A second anode/cathode layer of a second conductivity opposite to the first conductivity is formed on the intrinsic semiconductor layer and is electrically coupled to the second conductive via.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 21, 2007
    Applicant: Icemos Technology Corporation
    Inventors: Robin Wilson, Conor Brogan, Hugh Griffin, Cormac MacNamara
  • Publication number: 20070096240
    Abstract: A photodiode with a semiconductor intrinsic light absorption layer has at least one p-doped light absorption layer or an n-doped light absorption layer, and preferably both. The diode also has a cathode electrode and an anode electrode electrically coupled with the p-doped light absorption layer or the n-doped light absorption layer.
    Type: Application
    Filed: December 5, 2006
    Publication date: May 3, 2007
    Inventor: Jie YAO
  • Publication number: 20070096239
    Abstract: A semiconductor device includes a substrate comprising a material selected from the group consisting of AlN, SiC, GaN, sapphire and combinations thereof. An n+ type epitaxial layer is disposed above substrate and comprises GaN or AlGaN. An n? type epitaxial layer is disposed above substrate and comprises GaN or AlGaN. A p+-n junction grid comprising p+ GaN or p+ AlGaN is formed on selective areas of the n? type epitaxial layer. A metal layer is disposed over the p+-n junction grid and forms a Schottky contact. Another metal layer is deposited on one of the substrate and the n+ type epitaxial layer and forms a cathode electrode. A method of fabricating a semiconductor device is provided and includes forming a p+-n junction grid on a drift layer comprising GaN or AlGaN.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Xian-An Cao, Stephen Arthur
  • Patent number: 7205641
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 17, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 7202102
    Abstract: A photodiode with a semiconductor intrinsic light absorption layer has at least one p-doped light absorption layer or an n-doped light absorption layer, and preferably both. The diode also has a cathode electrode and an anode electrode electrically coupled with the p-doped light absorption layer or the n-doped light absorption layer.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: April 10, 2007
    Assignee: JDS Uniphase Corporation
    Inventor: Jie Yao
  • Publication number: 20070040233
    Abstract: A photovoltaic device includes at least a first electrode, a first-conductivity-type layer composed of non-single-crystalline silicon, a second-conductivity-type layer composed of polycrystalline silicon, a third-conductivity-type layer composed of non-single-crystalline silicon, and a second electrode, wherein the contact surface of the first electrode with respect to the first-conductivity-type layer has a shape interspersed with a plurality of projections, and the lower limit and the upper limit of the density of the projections interspersed on the surface of the first electrode satisfy the following equations, provided that the thickness of the second-conductivity-type layer is t ?m: Lower limit=0.312 exp(?0.60t) pieces/?m2 Upper limit=0.387 exp(?0.
    Type: Application
    Filed: August 14, 2006
    Publication date: February 22, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: TOSHIMITSU KARIYA
  • Publication number: 20070018268
    Abstract: The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is formed by combining a low doped first p-epitaxial layer, which has maximum thickness and doping concentration, placed upon a particularly high doped p substrate, with a low doped second n? epitaxial layer that borders the first layer, and n+ cathode of the pin photodiode being integrated into the second layer. The p areas delimit the second n epitaxial layer in a latent direction while another anode connecting area of the pin diode is provided on the rear face in addition to the anode connection.
    Type: Application
    Filed: November 12, 2003
    Publication date: January 25, 2007
    Applicant: X-Fab Semiconductor Foundries AG
    Inventors: Wolfgang Einbrodt, Horst Zimmerman, Michael Foertsch
  • Patent number: 7138697
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiging Ouyang, Jeremy D. Schaub
  • Publication number: 20060186503
    Abstract: An edge viewing semiconductor photodetector may be provided. Light may be transmitted through an optical fiber conduit comprising a core region surrounded by a cladding region. The light may be received at the edge viewing semiconductor photodetector having an active area. The active area may be substantially contained within a first plane. The edge viewing semiconductor photodetector may further have conducting contact pads connected to the active area. The contact pads may be substantially contained within plural planes. The first plane may have its normal direction substantially inclined with respect to a normal direction of the plural planes. The first plane may further have its normal direction substantially inclined with respect to a direction of the received light incident to the active area. Next, a signal may be received from the pads. The signal may correspond to the transmitted light.
    Type: Application
    Filed: February 22, 2006
    Publication date: August 24, 2006
    Inventors: Daniel Guidotti, Gee-Kung Chang, Jae-Hyun Ryou, Russell Dupuis