With Pn Homojunction Gate (epo) Patents (Class 257/E31.077)
  • Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Patent number: 7902622
    Abstract: A solid-state imaging device includes a photoelectric conversion section which is provided for each pixel and which converts light incident on a first surface of a substrate into signal charges, a circuit region which reads signal charges accumulated by the photoelectric conversion section, a multilayer film including an insulating film and a wiring film, the multilayer film being disposed on a second surface of the substrate opposite to the first surface, and a transmission-preventing film disposed at least between the wiring film in the multilayer film and the substrate.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: March 8, 2011
    Assignee: Sony Corporation
    Inventors: Masakazu Furukawa, Keiji Mabuchi
  • Patent number: 7902623
    Abstract: A solid-state imaging device includes a photoelectric conversion section which is provided for each pixel and which converts light incident on a first surface of a substrate into signal charges, a circuit region which reads signal charges accumulated by the photoelectric conversion section, a multilayer film including an insulating film and a wiring film, the multilayer film being disposed on a second surface of the substrate opposite to the first surface, and a transmission-preventing film disposed at least between the wiring film in the multilayer film and the substrate.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: March 8, 2011
    Assignee: Sony Corporation
    Inventors: Masakazu Furukawa, Keiji Mabuchi
  • Publication number: 20100224917
    Abstract: Disclosed is a solid-state image pickup apparatus including a semiconductor substrate, a photoelectric converter, a transfer gate, an insulating layer, a first silicon layer, and a pixel transistor portion. The photoelectric converter converts light energy of incident light into electrical energy and obtains a signal charge. The photoelectric converter is formed on a surface side in the semiconductor substrate. The transfer gate reads the signal charge from the photoelectric converter, and the transfer gate is formed on the semiconductor substrate adjacent to the photoelectric converter. The insulating layer is formed on the photoelectric converter in the semiconductor substrate. The first silicon layer is formed on the insulating layer. The pixel transistor portion amplifies and outputs the signal charge read by the transfer gate. The pixel transistor portion is formed on the insulating layer with the first silicon layer being an active region.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 9, 2010
    Applicant: Sony Corporation
    Inventor: Shinpei Yamaguchi
  • Publication number: 20100120190
    Abstract: A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A transistor directly connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern. Since the ion-implantation interrupting pattern is located on an upper portion of the gate electrode pattern of the transistor in the vicinity of the photo-detective device, a threshold voltage of the gate electrode pattern of the transistor in the vicinity of the photo-detective device is adjusted to a desired value.
    Type: Application
    Filed: January 22, 2010
    Publication date: May 13, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Duk-Min YI, Sung-Keun WON, Jun-Yeoul YOU
  • Publication number: 20090026511
    Abstract: A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.
    Type: Application
    Filed: August 22, 2008
    Publication date: January 29, 2009
    Inventors: Frederick Brady, Inna Patrick