Field-effect Type (e.g., Junction Field-effect Phototransistor) (epo) Patents (Class 257/E31.073)
  • Patent number: 11415609
    Abstract: The invention relates to a device for the frequency analysis of a signal, comprising a diamond crystal having NV centers defining sub-regions, an excitation unit for optically or electrically exciting each sub-region, an injection unit for injecting a signal so that the sub-region is in the presence of the signal, a magnetic field generator designed so as to generate a magnetic field on each sub-region, the magnetic field having a spatial variation of amplitude in a first direction, and a detector for detecting the resonance frequency of each sub-region of the region, the detector comprising an electrical contact for detecting the charges created in a sub-region, and a reading circuit.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: August 16, 2022
    Assignee: THALES
    Inventors: Thierry Debuisschert, Ludovic Mayer
  • Patent number: 8963274
    Abstract: A low noise infrared photo detector with a vertically integrated field effect transistor (FET) structure is formed without thermal diffusion. The FET structure includes a high sensitivity photo detector layer, a charge well layer, a transfer well layer, a charge transfer gate, and a drain electrode. In an embodiment, the photo detector layer and charge well are InGaAs and the other layers are InP layers.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Sensors Unlimited, Inc.
    Inventor: Peter Dixon
  • Patent number: 8928053
    Abstract: An input/output device includes a display circuit which changes its display state in accordance with a display data signal; a plurality of photodetector circuits which generate optical data in accordance with illuminance of light entering the photodetector circuits; wherein the photodetector circuits each include X (a natural number of 2 or more) photoelectric conversion elements; X charge accumulation control transistors in which one of a source and a drain is electrically connected to a second current terminal of one photoelectric conversion element of the X photoelectric conversion elements, and one charge accumulation control signal of X charge accumulation control signals from the photodetector circuit control section is input to the gate; and an amplifying transistor in which a gate is electrically connected to one of the source and the drain of each of the X charge accumulation control transistors.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8803273
    Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric R. Fossum, Dae-Kil Cha, Young-Gu Jin, Yoon-Dong Park, Soo-Jung Hwang
  • Patent number: 8779481
    Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide later is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: July 15, 2014
    Assignee: SRI International
    Inventor: James Robert Janesick
  • Patent number: 8680640
    Abstract: A solid-state imaging device includes semiconductor substrate; a plurality of photoelectric conversion sections of n-type that are formed at an upper part of semiconductor substrate and arranged in a matrix; output circuit that is formed on a charge detection surface that is one surface of semiconductor substrate and detects charges stored in photoelectric conversion sections; a plurality of isolating diffusion layers of a p-type that are formed under output circuit and include high concentration p-type layers adjacent to respective photoelectric conversion sections; and color filters formed on a light incident surface that is the other surface opposing the one surface of semiconductor substrate and transmit light with different wavelengths. Shapes of respective photoelectric conversion sections correspond to color filters and differ depending on the high concentration p-type layer configuring isolating diffusion layer.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: March 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Yutaka Hirose, Yoshihisa Kato
  • Patent number: 8664739
    Abstract: In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 4, 2014
    Assignee: Infrared Newco, Inc.
    Inventors: Clifford A. King, Conor S. Rafferty
  • Publication number: 20140027827
    Abstract: Pixel array structures to provide a ground contact for a CMOS pixel cell. In an embodiment, an active area of a pixel cell includes a photodiode disposed in a first portion of an active area, where a second portion of the active area extends from a side of the first portion. The second portion includes a doped region to provide a ground contact for the active area. In another embodiment, the pixel cell includes a transistor to transfer the charge from the photodiode, where a gate of the transistor is adjacent to the second portion and overlaps the side of the first portion.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Sohei Manabe, Jeong-Ho Lyu
  • Patent number: 8546901
    Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric R. Fossum, Dae-Kil Cha, Young-Gu Jin, Yoon-Dong Park, Soo-Jung Hwang
  • Patent number: 8519455
    Abstract: A light signal transfer device comprises a substrate having a gate dielectric layer; a source and drain doped regions formed in the substrate; a gate formed on the gate dielectric layer; a carbon nano-tube material formed under the gate dielectric layer to act a channel; and a photo-diode doped region formed adjacent to one of the source and drain doped regions, wherein the areas of the channel and the photo-diode doped region are fixed, the carbon nano-tube material reducing area of the channel and increase photo reception area for the photo-diode doped region to improve performance of the light signal transfer device.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: August 27, 2013
    Inventor: Kuo-Ching Chiang
  • Patent number: 8513675
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 20, 2013
    Assignee: Power Integrations, Inc.
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8508014
    Abstract: According to an aspect of the invention, a solid-state image sensor having a plurality of pixels includes a plurality of lower electrode, a photoelectric conversion layer, an upper electrode, a wiring portion and a plurality of connection portions. The plurality of lower electrodes respectively corresponds to the plurality of pixels. The photoelectric conversion layer is stacked on the lower electrodes. The upper electrode is stacked on the photoelectric conversion layer. The wiring portion supplies, to the upper electrode, a voltage to generate an electric field between the upper electrode and the lower electrode. The plurality of connection portions connects the wiring portion and the upper electrode. The plurality of connection portions are disposed in a circumference region which is a region other than a sensor region in which a plurality of photoelectric conversion elements are arranged. The plurality of connection portions is disposed in a symmetrical arrangement.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: August 13, 2013
    Assignee: Fujifilm Corporation
    Inventor: Takuya Takata
  • Patent number: 8502290
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 6, 2013
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Patent number: 8471312
    Abstract: Disclosed is a solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 25, 2013
    Assignee: Sony Corporation
    Inventor: Yoshiharu Kudoh
  • Patent number: 8415720
    Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 9, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Badih El-Kareh, Kyu Ok Lee, Joo Hyung Kim, Jung Joo Kim
  • Patent number: 8415713
    Abstract: This invention provides a photo-FET, in which a FET part and photodiode part are stacked, and the FET part and photodiode part are optimized independently in design and operational bias conditions. The semiconductor layer serving as a photo-absorption layer (41) is formed on the cathode semiconductor layer (10) of a photodiode part (50). An electron barrier layer (40) with a wider bandgap semiconductor than a photo-absorption layer (41), which also serves as an anode layer of a photodiode part (50), is formed on a photo-absorption layer (41). The channel layer (15) which constitutes the channel regions of the FET part is formed with a narrower bandgap semiconductor than an electron barrier layer (40) on an electron barrier layer (40). The hole barrier layer (16) with a bandgap wider than the semiconductor which constitutes a channel layer (15) is formed on a channel layer (15). The source electrode (30) and drain electrode (32) which are separated each others, are formed on a hole barrier layer (16).
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: April 9, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Mutsuo Ogura
  • Publication number: 20130056807
    Abstract: A photoelectric converting apparatus has first and third semiconductor layers of a first conductivity type which respectively output signals obtained by photoelectric conversion, and second and fourth semiconductor layers of a second conductivity type supplied with potentials from a potential supplying unit. In the photoelectric converting apparatus, the first, second, third and fourth semiconductor layers are arranged in sequence, the second and fourth semiconductor layers are electrically separated from each other, and the potential to be supplied to the second semiconductor layer and the potential to be supplied to the fourth semiconductor layer are controlled independently from each other.
    Type: Application
    Filed: August 27, 2012
    Publication date: March 7, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hideo Kobayashi, Tetsunobu Kochi
  • Patent number: 8389319
    Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide layer is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: March 5, 2013
    Assignee: SRI International
    Inventor: James Robert Janesick
  • Patent number: 8368122
    Abstract: A multiple-junction photoelectric device includes a substrate with a first conducting layer thereon, at least two elementary photoelectric devices of p-i-n or p-n configuration, with a second conducting layer thereon, and at least one intermediate layer between two adjacent elementary photoelectric devices. The intermediate layer has, on the incoming light side, opposite top and bottom faces, the top and bottom faces having respectively a surface morphology including inclined elementary surfaces so ?90bottom is smaller than ?90top by at least 3°, preferably 6°, more preferably 10°, and even more preferably 15°; where ?90top is the angle for which 90% of the elementary surfaces of the top face of the intermediate layer have an inclination equal to or less than this angle, and ?90bottom is the angle for which 90% of the elementary surfaces of the bottom face of the intermediate layer have an inclination equal to or less than this angle.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: February 5, 2013
    Assignee: Universite de Neuchatel
    Inventors: Didier Domine, Peter Cuony, Julien Bailat
  • Patent number: 8344432
    Abstract: A solid state imaging device includes: a light receiving section performing photoelectric conversion; a transfer register formed in a semiconductor base; a transfer electrode formed of a semiconductor layer on the transfer register; a charge transfer section which formed of the transfer register and the transfer electrode and transferring a signal charge accumulated in the light receiving section; a bus line electrically connected to a portion of the transfer electrode to supply a driving pulse to the transfer electrode and formed of a metal layer; and a barrier metal layer formed near an interface between the transfer electrode and the bus line in a contact section that connects the transfer electrode and the bus line with each other and having a work function of the size between a work function of the semiconductor layer of the transfer electrode and a work function of the metal layer of the bus line.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: January 1, 2013
    Assignee: Sony Corporation
    Inventor: Fuminobu Saiho
  • Patent number: 8319262
    Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: November 27, 2012
    Assignee: SRI International
    Inventor: James Robert Janesick
  • Patent number: 8299484
    Abstract: An optoelectronic semiconductor chip including a radiation passage area, where a contact metallization is applied to the radiation passage area, and a first reflective layer sequence is applied to that surface of the contact metallization which is remote from the radiation passage area, and an optoelectronic component that includes such a chip.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: October 30, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Grötsch, Norbert Linder
  • Patent number: 8293629
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 23, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Publication number: 20120235212
    Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Gang Chen, Sing-Chung Hu, Duli Mao, Hsin-Chih Tai, Yin Qian, Vincent Venezia, Rongsheng Yang, Howard E. Rhodes
  • Publication number: 20120199892
    Abstract: A light signal transfer device comprises a substrate having a gate dielectric layer; a source and drain doped regions formed in the substrate; a gate formed on the gate dielectric layer; a carbon nano-tube material formed under the gate dielectric layer to act a channel; and a photo-diode doped region formed adjacent to one of the source and drain doped regions, wherein the areas of the channel and the photo-diode doped region are fixed, the carbon nano-tube material reducing area of the channel and increase photo reception area for the photo-diode doped region to improve performance of the light signal transfer device.
    Type: Application
    Filed: March 14, 2012
    Publication date: August 9, 2012
    Inventor: Kuo-Ching CHIANG
  • Publication number: 20120199882
    Abstract: Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Inventor: Jong-Cheol Shin
  • Patent number: 8202772
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: June 19, 2012
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Publication number: 20120147286
    Abstract: The light use efficiency of a thin film diode is improved even when the semiconductor layer of the diode has a small thickness, thereby improving the light detection sensitivity of the diode. A thin film diode (130) having a first semiconductor layer (131) including, at least, an n-type region (131n) and a p-type region (131p) is provided on one side of a substrate (101), and a light-blocking layer (160) is provided between the substrate and the first semiconductor layer. Asperities are provided on the side of the light-blocking layer facing the first semiconductor layer. The first semiconductor layer has a geometry of asperities conforming with the asperities on the light-blocking layer. Light incident on the light-blocking layer is diffusely reflected and enters the first semiconductor layer.
    Type: Application
    Filed: July 22, 2010
    Publication date: June 14, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihiro Oda, Makoto Nakazawa
  • Publication number: 20120146115
    Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel
  • Publication number: 20120146027
    Abstract: An adverse effect of parasitic capacitance on optical data output from a photodetector circuit is suppressed. A photodetector circuit includes a photoelectric conversion element; a first field-effect transistor; a second field-effect transistor; a first conductive layer functioning as a gate of the first field-effect transistor; an insulating layer provided over the first conductive layer; a semiconductor layer overlapping with the first conductive layer with the insulating layer interposed therebetween; a second conductive layer electrically connected to the semiconductor layer; and a third conductive layer electrically connected to the semiconductor layer, whose pair of side surfaces facing each other overlaps with at least one conductive layer including the first conductive layer with the insulating layer interposed therebetween, and which functions as the other of the source and the drain of the first field-effect transistor.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 14, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hikaru TAMURA, Yoshiyuki KUROKAWA, Takayuki IKEDA
  • Publication number: 20120104238
    Abstract: To provide a photoelectric conversion device with low power consumption and a method for operating the photoelectric conversion device. The photoelectric conversion device includes a charge storage capacitor portion, a photodiode, and a plurality of transistors. The charge storage capacitor portion is charged after being reset. Then, the charge storage capacitor portion is discharged through the photodiode or a current mirror circuit connected to the photodiode for a given period of time, and after that, the potential of the charge storage capacitor portion is read. Since power is consumed only at the time of charging, power consumption can be reduced.
    Type: Application
    Filed: October 20, 2011
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Atsushi HIROSE
  • Publication number: 20120080732
    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. ANDERSON, Mark D. JAFFE
  • Patent number: 8138532
    Abstract: The objective of this invention is to provide a semiconductor device containing a photodiode and having stable, high sensitivity with respect to short wavelength light near 405 nm, and a manufacturing method for said semiconductor device. PIN photodiode (100C) has the following layers formed on silicon substrate (110): p-type silicon region (112), n-type silicon layer (114), field oxide film (118), silicon oxide film (120c) that covers the surface of the active region, and silicon nitride film (122c) that covers silicon oxide film (120c). Said field oxide film (118) contains extending portions (160) extending to the interior of the active region; the side portions of extending portions (160) are connected to silicon oxide film (120c), and the exposed surface portions of extending portions (160) become regions for hydrogen diffusion.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroyuki Tomomatsu, Yukihisa Hirotsugu
  • Publication number: 20120032169
    Abstract: The present invention relates to a visible ray sensor and a light sensor capable of improving photosensitivity by preventing photodegradation. The visible ray sensor may include: a substrate, a light blocking member formed on the substrate, and a visible ray sensing thin film transistor formed on the light blocking member. The light blocking member may be made of a transparent electrode, a band pass filter, or an opaque metal.
    Type: Application
    Filed: December 28, 2010
    Publication date: February 9, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-Youn Han, Jun-Ho Song, Kyung-Sook Jeon, Mi-Seon Seo, Sung-Hoon Yang, Suk-Won Jung, Seung Mi Seo
  • Publication number: 20120025275
    Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 2, 2012
    Inventor: Shen Wang
  • Patent number: 8093633
    Abstract: A semiconductor device includes a conducting channel (130) formed beneath a substrate surface with a pre-determined photo-conductivity spectral response. The channel is formed between two pn-junctions (126, 128) defining first and third photo-electric depletion regions at respective depths relative to the surface corresponding to penetration depths of light of different wavelengths. The first region (106) which has the light absorbing surface (104) above the first pn-junction (126) is specific to a first color. The channel region (130) between the two pn-junctions (126, 128) is photo-conductive to a second color. The third region below the second pn-junction (128) is sensitive to a third color. Electrical contacts (118, 120, 122, 124) are disposed on the source (112), the top gate (106), the drain (114) and the bottom gate (116) for receiving the electrical currents induced by the presence of the absorbed wavelengths.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: January 10, 2012
    Assignee: Nanyang Technological University
    Inventors: Daniel Pulu Poenar, Mihaela Carp
  • Patent number: 8084790
    Abstract: An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: December 27, 2011
    Assignee: Tong Hsing Electronic Industries, Inc.
    Inventors: Chi-Chih Huang, Chih-Yang Hsu
  • Patent number: 8058655
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 15, 2011
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8058657
    Abstract: A thin film transistor comprises: a first transistor region and a second transistor region defined on a substrate; and a first transistor and a second transistor respectively disposed on the first and second transistor regions, the first transistor comprising: a first semiconductor layer having source, channel, and drain regions defined on the substrate; a first insulating film disposed on the first semiconductor layer; a first transparent electrode disposed on the first insulating film and formed corresponding to the channel region of the first semiconductor layer; and a second insulating film disposed on the first transparent electrode, and the second transistor comprising: a second semiconductor layer having source, channel, and drain regions defined on the substrate; the first insulating film disposed on the second semiconductor layer; a second transparent electrode disposed on the first insulating film and formed corresponding to the channel region of the second semiconductor layer; a second gate dispose
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: November 15, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Younghak Lee, Jaemin Seok
  • Patent number: 8048705
    Abstract: A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jieguang Huo, Jianping Yang
  • Publication number: 20110241090
    Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Patent number: 8026565
    Abstract: A thin film semiconductor in the form of a metal semiconductor field effect transistor, includes a substrate 10 of paper sheet material and a number of thin film active inorganic layers that are deposited in layers on the substrate. The active layers are printed using an offset lithography printing process. A first active layer comprises source 12.1 and drain 12.2 conductors of colloidal silver ink, that are printed directly onto the paper substrate. A second active layer is an intrinsic semiconductor layer 14 of colloidal nanocrystalline silicon ink which is printed onto the first layer. A third active layer comprises a metallic conductor 16 of colloidal silver which is printed onto the second layer to form a gate electrode. This invention extends to other thin film semiconductors such as photovoltaic cells and to a method of manufacturing semiconductors.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: September 27, 2011
    Assignee: University of Cape Town
    Inventors: Margit Harting, David Thomas Britton
  • Publication number: 20110220971
    Abstract: Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 15, 2011
    Applicant: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Jutao Jiang, Jeffrey McKee, Drake Miller, Chintamani Palsule, Leonard Forbes
  • Publication number: 20110215227
    Abstract: The present invention relates to a photosensitive detector with a composite dielectric gate MOSFET structure and its signal readout method. The MOSFET structure detector is formed on a p-type semiconductor substrate. N-type semiconductor regions locate on the two sides of the top part of the p-type semiconductor substrate to form a source and a drain. An underlying dielectric layer, a photo-electron storage layer, a top dielectric layer, and a control gate are stacked on the substrate in sequence. The top insulating dielectric layer can prevent the photoelectrons stored in the photo-electron storage layer from leaking into the control gate. The source and the drain are floating when photoelectrons are collected and injected into the photoelectron storing layer to be held therein. There is a transparent or semi-transparent window for detecting incident light forming on the substrate or gate surface.
    Type: Application
    Filed: February 10, 2010
    Publication date: September 8, 2011
    Applicants: NANJING UNIVERSITY
    Inventors: Feng Yan, Rong Zhang, Yi Shi, Lin Pu, Yue Xu, Fuwei Wu, Xiaofeng Bo, Haoguang Xia
  • Publication number: 20110216231
    Abstract: A pixel cell and imaging arrays using the same are disclosed. The pixel cell includes a photodiode that is connected to a floating diffusion node by a transfer gate that couples the photodiode to the floating diffusion node in response to a first gate signal. A shielding electrode shields the floating diffusion node from the first gate signal. An output stage generates a signal related to a charge on the floating diffusion node. In one aspect of the invention, the photodiode is connected to the floating diffusion node by a buried channel, and the shielding electrode includes an electrode overlying the channel and positioned between the transfer gate and the floating diffusion node. The shielding electrode is held at a potential that prevents charge from accumulating under the shielding electrode when the floating diffusion is at the second potential.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 8, 2011
    Inventor: Boyd Fowler
  • Publication number: 20110181749
    Abstract: A solid-state imaging device includes multiple pixels formed of photoelectric converters and pixel transistors; a floating diffusion portion that exists within a region of each of the photoelectric converters when viewed from above; and a vertical transfer gate electrode of a transfer transistor that surrounds at least a portion of each photoelectric converter and is formed in the depth direction of a substrate and makes up the pixel transistor.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Applicant: SONY CORPORATION
    Inventor: Akihiro Yamada
  • Publication number: 20110122108
    Abstract: It is an object to perform imaging a high-resolution image in a display device including a photosensor regardless of the intensity of incident light on the photosensor. A display device including a display panel which is provided a photosensor and having a function of imaging by a change of the sensitivity of the photosensor in accordance with the incident light is provided. The sensitivity of the photosensor is improved when the intensity of the incident light is low, so that the imaging accuracy is improved; therefore, misperception of contact is prevented and an obtained image can be clear.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 26, 2011
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda
  • Publication number: 20110115043
    Abstract: According to an aspect of the invention, a solid-state image sensor having a plurality of pixels includes a plurality of lower electrode, a photoelectric conversion layer, an upper electrode, a wiring portion and a plurality of connection portions. The plurality of lower electrodes respectively corresponds to the plurality of pixels. The photoelectric conversion layer is stacked on the lower electrodes. The upper electrode is stacked on the photoelectric conversion layer. The wiring portion supplies, to the upper electrode, a voltage to generate an electric field between the upper electrode and the lower electrode. The plurality of connection portions connects the wiring portion and the upper electrode. The plurality of connection portions are disposed in a circumference region which is a region other than a sensor region in which a plurality of photoelectric conversion elements are arranged. The plurality of connection portions is disposed in a symmetrical arrangement.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 19, 2011
    Applicant: FUJIFILM CORPORATION
    Inventor: Takuya TAKATA
  • Patent number: 7936039
    Abstract: A pixel for a CMOS photo sensor with increased full well capacity is disclosed. The pixel having a photosensitive element, a photo gate, potential well and a readout circuit. The photosensitive element having a front side and a back side, for releasing charge when light strikes the back side of the photosensitive element. The potential well receives the released charge from the photosensitive element. The photo gate located on the front side of the photosensitive element, for transferring the released charge from the potential well to a sense node. The readout circuit coupled to the sense node, for measuring a voltage corresponding to the released charge transferred to the sense node.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 3, 2011
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Stefan Clemens Lauxtermann
  • Publication number: 20110089311
    Abstract: An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Vincent Venezia, Hsin-Chih Tai, Duli Mao, Howard E. Rhodes