With Pn Heterojunction Gate (epo) Patents (Class 257/E31.08)
  • Patent number: 8383443
    Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., John J. Ellis-Monaghan, Edward J. Nowak
  • Patent number: 8048705
    Abstract: A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jieguang Huo, Jianping Yang
  • Patent number: 7132677
    Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 7, 2006
    Assignee: Dongguk University
    Inventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung